Regfile: Rename signals for correct pipe stages.

diff --git a/Decode.v b/Decode.v
index 3eecd55ef147d6e72f21b59b44ab378165c029da..7accb9d4c130735f2b99ea5277248eab6f508738 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -3,8 +3,8 @@
 module Decode(
        input clk,
        input stall,
 module Decode(
        input clk,
        input stall,

-       input [31:0] insn,
-       input [31:0] inpc,
+       input [31:0] insn_1a,
+       input [31:0] pc_1a,

        input [31:0] incpsr,
        input [31:0] inspsr,
        output reg [31:0] op0,
        input [31:0] incpsr,
        input [31:0] inspsr,
        output reg [31:0] op0,


@@ -14,12 +14,12 @@ module Decode(
        output reg [31:0] outcpsr,
        output reg [31:0] outspsr,
 
        output reg [31:0] outcpsr,
        output reg [31:0] outspsr,
 

-       output reg [3:0] read_0,
-       output reg [3:0] read_1,
-       output reg [3:0] read_2,
-       input [31:0] rdata_0,
-       input [31:0] rdata_1,
-       input [31:0] rdata_2
+       output reg [3:0] rf__read_0_1a,
+       output reg [3:0] rf__read_1_1a,
+       output reg [3:0] rf__read_2_1a,
+       input [31:0] rf__rdata_0_1a,
+       input [31:0] rf__rdata_1_1a,
+       input [31:0] rf__rdata_2_1a

        );
 
        wire [31:0] regs0, regs1, regs2;
        );
 
        wire [31:0] regs0, regs1, regs2;


@@ -33,23 +33,23 @@ module Decode(
        wire shift_cflag_out;
        wire [31:0] rotate_res;
 
        wire shift_cflag_out;
        wire [31:0] rotate_res;
 

-       assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
-       assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
-       assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
+       assign regs0 = (rf__read_0_1a == 4'b1111) ? rpc : rf__rdata_0_1a;
+       assign regs1 = (rf__read_1_1a == 4'b1111) ? rpc : rf__rdata_1_1a;
+       assign regs2 = rf__rdata_2_1a; /* use regs2 for things that cannot be r15 */

 
 

-       IREALLYHATEARMSHIFT shift(.insn(insn),
+       IREALLYHATEARMSHIFT shift(.insn(insn_1a),

                                  .operand(regs1),
                                  .reg_amt(regs2),
                                  .cflag_in(incpsr[`CPSR_C]),
                                  .res(shift_res),
                                  .cflag_out(shift_cflag_out));
 
                                  .operand(regs1),
                                  .reg_amt(regs2),
                                  .cflag_in(incpsr[`CPSR_C]),
                                  .res(shift_res),
                                  .cflag_out(shift_cflag_out));
 

-       SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
-                             .amt(insn[11:8]),
+       SuckLessRotator whirr(.oper({24'b0, insn_1a[7:0]}),
+                             .amt(insn_1a[11:8]),

                              .res(rotate_res));
 
        always @(*)
                              .res(rotate_res));
 
        always @(*)

-               casez (insn)
+               casez (insn_1a)

                `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 //             `DECODE_ALU_MUL_LONG,           /* Multiply long */
                `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
                `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 //             `DECODE_ALU_MUL_LONG,           /* Multiply long */
                `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */


@@ -66,75 +66,75 @@ module Decode(
                `DECODE_LDCSTC,                 /* Coprocessor data transfer */
                `DECODE_CDP,                    /* Coprocessor data op */
                `DECODE_SWI:                    /* SWI */
                `DECODE_LDCSTC,                 /* Coprocessor data transfer */
                `DECODE_CDP,                    /* Coprocessor data op */
                `DECODE_SWI:                    /* SWI */

-                       rpc = inpc + 8;
+                       rpc = pc_1a + 8;

                `DECODE_MRCMCR:                 /* Coprocessor register transfer */
                `DECODE_MRCMCR:                 /* Coprocessor register transfer */

-                       rpc = inpc + 12;
+                       rpc = pc_1a + 12;

                `DECODE_ALU:                    /* ALU */
                `DECODE_ALU:                    /* ALU */

-                       rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
+                       rpc = pc_1a + (insn_1a[25] ? 8 : (insn_1a[4] ? 12 : 8));

                default:                        /* X everything else out */
                        rpc = 32'hxxxxxxxx;
                endcase
        
        always @(*) begin
                default:                        /* X everything else out */
                        rpc = 32'hxxxxxxxx;
                endcase
        
        always @(*) begin

-               read_0 = 4'hx;
-               read_1 = 4'hx;
-               read_2 = 4'hx;
+               rf__read_0_1a = 4'hx;
+               rf__read_1_1a = 4'hx;
+               rf__read_2_1a = 4'hx;

                
                

-               casez (insn)
+               casez (insn_1a)

                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin

-                       read_0 = insn[15:12]; /* Rn */
-                       read_1 = insn[3:0];   /* Rm */
-                       read_2 = insn[11:8];  /* Rs */
+                       rf__read_0_1a = insn_1a[15:12]; /* Rn */
+                       rf__read_1_1a = insn_1a[3:0];   /* Rm */
+                       rf__read_2_1a = insn_1a[11:8];  /* Rs */

                end
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin end
                `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
                end
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin end
                `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */

-                       read_0 = insn[3:0];     /* Rm */
+                       rf__read_0_1a = insn_1a[3:0];   /* Rm */

                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */

-                       read_0 = insn[3:0];     /* Rm */
+                       rf__read_0_1a = insn_1a[3:0];   /* Rm */

                `DECODE_ALU_SWP:        /* Atomic swap */
                begin
                `DECODE_ALU_SWP:        /* Atomic swap */
                begin

-                       read_0 = insn[19:16]; /* Rn */
-                       read_1 = insn[3:0];   /* Rm */
+                       rf__read_0_1a = insn_1a[19:16]; /* Rn */
+                       rf__read_1_1a = insn_1a[3:0];   /* Rm */

                end
                `DECODE_ALU_BX:         /* Branch and exchange */
                end
                `DECODE_ALU_BX:         /* Branch and exchange */

-                       read_0 = insn[3:0];   /* Rn */
+                       rf__read_0_1a = insn_1a[3:0];   /* Rn */

                `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
                begin
                `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
                begin

-                       read_0 = insn[19:16];
-                       read_1 = insn[3:0];
-                       read_2 = insn[15:12];
+                       rf__read_0_1a = insn_1a[19:16];
+                       rf__read_1_1a = insn_1a[3:0];
+                       rf__read_2_1a = insn_1a[15:12];

                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin

-                       read_0 = insn[19:16];
-                       read_1 = insn[15:12];
+                       rf__read_0_1a = insn_1a[19:16];
+                       rf__read_1_1a = insn_1a[15:12];

                end
                `DECODE_ALU:            /* ALU */
                begin
                end
                `DECODE_ALU:            /* ALU */
                begin

-                       read_0 = insn[19:16]; /* Rn */
-                       read_1 = insn[3:0];   /* Rm */
-                       read_2 = insn[11:8];  /* Rs for shift */
+                       rf__read_0_1a = insn_1a[19:16]; /* Rn */
+                       rf__read_1_1a = insn_1a[3:0];   /* Rm */
+                       rf__read_2_1a = insn_1a[11:8];  /* Rs for shift */

                end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
                begin end
                `DECODE_LDRSTR:         /* Single data transfer */
                begin
                end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
                begin end
                `DECODE_LDRSTR:         /* Single data transfer */
                begin

-                       read_0 = insn[19:16]; /* Rn */
-                       read_1 = insn[3:0];   /* Rm */
-                       read_2 = insn[15:12];
+                       rf__read_0_1a = insn_1a[19:16]; /* Rn */
+                       rf__read_1_1a = insn_1a[3:0];   /* Rm */
+                       rf__read_2_1a = insn_1a[15:12];

                end
                `DECODE_LDMSTM:         /* Block data transfer */
                end
                `DECODE_LDMSTM:         /* Block data transfer */

-                       read_0 = insn[19:16];
+                       rf__read_0_1a = insn_1a[19:16];

                `DECODE_BRANCH:         /* Branch */
                begin end
                `DECODE_LDCSTC:         /* Coprocessor data transfer */
                `DECODE_BRANCH:         /* Branch */
                begin end
                `DECODE_LDCSTC:         /* Coprocessor data transfer */

-                       read_0 = insn[19:16];
+                       rf__read_0_1a = insn_1a[19:16];

                `DECODE_CDP:            /* Coprocessor data op */
                begin end
                `DECODE_MRCMCR:         /* Coprocessor register transfer */
                `DECODE_CDP:            /* Coprocessor data op */
                begin end
                `DECODE_MRCMCR:         /* Coprocessor register transfer */

-                       read_0 = insn[15:12];
+                       rf__read_0_1a = insn_1a[15:12];

                `DECODE_SWI:            /* SWI */
                begin end
                default:
                `DECODE_SWI:            /* SWI */
                begin end
                default:


@@ -148,7 +148,7 @@ module Decode(
                op2_out = 32'hxxxxxxxx;
                carry_out = 1'bx;
                
                op2_out = 32'hxxxxxxxx;
                carry_out = 1'bx;
                

-               casez (insn)
+               casez (insn_1a)

                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                        op0_out = regs0;
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                        op0_out = regs0;


@@ -160,7 +160,7 @@ module Decode(
                `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
                        op0_out = regs0;
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
                        op0_out = regs0;
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */

-                       if(insn[25]) begin     /* the constant case */
+                       if(insn_1a[25]) begin     /* the constant case */

                                op0_out = rotate_res;
                        end else begin
                                op0_out = regs0;
                                op0_out = rotate_res;
                        end else begin
                                op0_out = regs0;


@@ -181,13 +181,13 @@ module Decode(
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        op0_out = regs0;
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        op0_out = regs0;

-                       op1_out = {24'b0, insn[11:8], insn[3:0]};
+                       op1_out = {24'b0, insn_1a[11:8], insn_1a[3:0]};

                        op2_out = regs1;
                end
                `DECODE_ALU:            /* ALU */
                begin
                        op0_out = regs0;
                        op2_out = regs1;
                end
                `DECODE_ALU:            /* ALU */
                begin
                        op0_out = regs0;

-                       if(insn[25]) begin     /* the constant case */
+                       if(insn_1a[25]) begin     /* the constant case */

                                carry_out = incpsr[`CPSR_C];
                                op1_out = rotate_res;
                        end else begin
                                carry_out = incpsr[`CPSR_C];
                                op1_out = rotate_res;
                        end else begin


@@ -198,8 +198,8 @@ module Decode(
                `DECODE_LDRSTR:         /* Single data transfer */
                begin
                        op0_out = regs0;
                `DECODE_LDRSTR:         /* Single data transfer */
                begin
                        op0_out = regs0;

-                       if(!insn[25] /* immediate */) begin
-                               op1_out = {20'b0, insn[11:0]};
+                       if(!insn_1a[25] /* immediate */) begin
+                               op1_out = {20'b0, insn_1a[11:0]};

                                carry_out = incpsr[`CPSR_C];
                        end else begin
                                op1_out = shift_res;
                                carry_out = incpsr[`CPSR_C];
                        end else begin
                                op1_out = shift_res;


@@ -210,14 +210,14 @@ module Decode(
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                        op0_out = regs0;
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                        op0_out = regs0;

-                       op1_out = {16'b0, insn[15:0]};
+                       op1_out = {16'b0, insn_1a[15:0]};

                end
                `DECODE_BRANCH:         /* Branch */
                end
                `DECODE_BRANCH:         /* Branch */

-                       op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
+                       op0_out = {{6{insn_1a[23]}}, insn_1a[23:0], 2'b0};

                `DECODE_LDCSTC:         /* Coprocessor data transfer */
                begin
                        op0_out = regs0;
                `DECODE_LDCSTC:         /* Coprocessor data transfer */
                begin
                        op0_out = regs0;

-                       op1_out = {24'b0, insn[7:0]};
+                       op1_out = {24'b0, insn_1a[7:0]};

                end
                `DECODE_CDP:            /* Coprocessor data op */
                begin end
                end
                `DECODE_CDP:            /* Coprocessor data op */
                begin end

diff --git a/Issue.v b/Issue.v
index 07c709d7ae4aa9335f21122ac12e9dc3f2f47a09..9fb30778d6062bcb91d98fc0456339c71b5949f7 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -7,9 +7,9 @@ module Issue(
        input stall,    /* pipeline control */
        input flush,    /* XXX not used yet */
        
        input stall,    /* pipeline control */
        input flush,    /* XXX not used yet */
        

-       input inbubble, /* stage inputs */
-       input [31:0] insn,
-       input [31:0] inpc,
+       input bubble_1a,        /* stage inputs */
+       input [31:0] insn_1a,
+       input [31:0] pc_1a,

        input [31:0] cpsr,
        
        output wire outstall,   /* stage outputs */
        input [31:0] cpsr,
        
        output wire outstall,   /* stage outputs */


@@ -21,7 +21,7 @@ module Issue(
        
 `ifdef COPY_PASTA_FODDER
        /* from page 2 of ARM7TDMIvE2.pdf */
        
 `ifdef COPY_PASTA_FODDER
        /* from page 2 of ARM7TDMIvE2.pdf */

-       casex (insn)
+       casex (insn_1a)

        `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 //     `DECODE_ALU_MUL_LONG:   /* Multiply long */
        `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
        `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 //     `DECODE_ALU_MUL_LONG:   /* Multiply long */
        `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */


@@ -58,17 +58,17 @@ module Issue(
                        idxbit = (16'b1) << r;
        endfunction
        
                        idxbit = (16'b1) << r;
        endfunction
        

-       wire [3:0] rn = insn[19:16];
-       wire [3:0] rd = insn[15:12];
-       wire [3:0] rs = insn[11:8];
-       wire [3:0] rm = insn[3:0];
-       wire [3:0] cond = insn[31:28];
+       wire [3:0] rn = insn_1a[19:16];
+       wire [3:0] rd = insn_1a[15:12];
+       wire [3:0] rs = insn_1a[11:8];
+       wire [3:0] rm = insn_1a[3:0];
+       wire [3:0] cond = insn_1a[31:28];

        
        

-       wire [3:0] rd_mul = insn[19:16];
-       wire [3:0] rn_mul = insn[15:12];
-       wire [3:0] rs_mul = insn[11:8];
+       wire [3:0] rd_mul = insn_1a[19:16];
+       wire [3:0] rn_mul = insn_1a[15:12];
+       wire [3:0] rs_mul = insn_1a[11:8];

        
        

-       wire [3:0] alu_opc = insn[24:21];
+       wire [3:0] alu_opc = insn_1a[24:21];

        
        function alu_is_logical;
                input [3:0] op;
        
        function alu_is_logical;
                input [3:0] op;


@@ -100,18 +100,18 @@ module Issue(
        endfunction
        
        always @(*)
        endfunction
        
        always @(*)

-               casez (insn)
+               casez (insn_1a)

                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
-                       def_cpsr = insn[20] /* setcc */;
+                       use_regs = (insn_1a[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
+                       def_cpsr = insn_1a[20] /* setcc */;

                        def_regs = idxbit(rd_mul);
                end
 //             `DECODE_ALU_MUL_LONG:   /* Multiply long */
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin
                        def_regs = idxbit(rd_mul);
                end
 //             `DECODE_ALU_MUL_LONG:   /* Multiply long */
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin

-                       use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */;
+                       use_cpsr = `COND_MATTERS(cond) || (insn_1a[22] == 0) /* Source = CPSR */;

                        use_regs = 0;
                        def_cpsr = 0;
                        def_regs = idxbit(rd);
                        use_regs = 0;
                        def_cpsr = 0;
                        def_regs = idxbit(rd);


@@ -126,7 +126,7 @@ module Issue(
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = insn[25] ? 0 : idxbit(rm);
+                       use_regs = insn_1a[25] ? 0 : idxbit(rm);

                        def_cpsr = 1;
                        def_regs = 0;
                end
                        def_cpsr = 1;
                        def_regs = 0;
                end


@@ -147,27 +147,27 @@ module Issue(
                `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       use_regs = idxbit(rn) | idxbit(rm) | (insn_1a[20] /* L */ ? 0 : idxbit(rd));

                        def_cpsr = 0;
                        def_cpsr = 0;

-                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+                       def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;

                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       use_regs = idxbit(rn) | (insn_1a[20] /* L */ ? 0 : idxbit(rd));

                        def_cpsr = 0;
                        def_cpsr = 0;

-                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+                       def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;

                end
                `DECODE_ALU:    /* ALU */
                begin
                end
                `DECODE_ALU:    /* ALU */
                begin

-                       use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
+                       use_cpsr = `COND_MATTERS(cond) | (!insn_1a[25] /* I */ && shift_requires_carry(insn_1a[11:4]));

                        use_regs =
                        use_regs =

-                               (insn[25] /* I */ ? 0 :
-                                       (insn[4] /* shift by reg */ ?
+                               (insn_1a[25] /* I */ ? 0 :
+                                       (insn_1a[4] /* shift by reg */ ?

                                                (idxbit(rs) | idxbit(rm)) :
                                                (idxbit(rm)))) |
                                (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
                                                (idxbit(rs) | idxbit(rm)) :
                                                (idxbit(rm)))) |
                                (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);

-                       def_cpsr = insn[20] /* S */;
+                       def_cpsr = insn_1a[20] /* S */;

                        def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
                end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
                        def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
                end
                `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */


@@ -180,30 +180,30 @@ module Issue(
                `DECODE_LDRSTR:
                begin
                        use_cpsr = `COND_MATTERS(cond);
                `DECODE_LDRSTR:
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd));
+                       use_regs = idxbit(rn) | (insn_1a[25] /* I */ ? idxbit(rm) : 0) | (insn_1a[20] /* L */ ? 0 : idxbit(rd));

                        def_cpsr = 0;
                        def_cpsr = 0;

-                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+                       def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;

                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]);
-                       def_cpsr = insn[22];    /* This is a superset of all cases, anyway. */
-                       def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0);
+                       use_regs = idxbit(rn) | (insn_1a[20] /* L */ ? 0 : insn_1a[15:0]);
+                       def_cpsr = insn_1a[22]; /* This is a superset of all cases, anyway. */
+                       def_regs = (insn_1a[21] /* W */ ? idxbit(rn) : 0) | (insn_1a[20] /* L */ ? insn_1a[15:0] : 0);

                end
                `DECODE_BRANCH: /* Branch */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = 0;
                        def_cpsr = 0;
                end
                `DECODE_BRANCH: /* Branch */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = 0;
                        def_cpsr = 0;

-                       def_regs = insn[24] /* L */ ? (16'b1 << 14) : 0;
+                       def_regs = insn_1a[24] /* L */ ? (16'b1 << 14) : 0;

                end
                `DECODE_LDCSTC: /* Coprocessor data transfer */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = idxbit(rn);
                        def_cpsr = 0;
                end
                `DECODE_LDCSTC: /* Coprocessor data transfer */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                        use_regs = idxbit(rn);
                        def_cpsr = 0;

-                       def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
+                       def_regs = insn_1a[21] /* W */ ? idxbit(rn) : 0;

                end
                `DECODE_CDP:    /* Coprocessor data op */
                begin
                end
                `DECODE_CDP:    /* Coprocessor data op */
                begin


@@ -215,9 +215,9 @@ module Issue(
                `DECODE_MRCMCR:         /* Coprocessor register transfer */
                begin
                        use_cpsr = `COND_MATTERS(cond);
                `DECODE_MRCMCR:         /* Coprocessor register transfer */
                begin
                        use_cpsr = `COND_MATTERS(cond);

-                       use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
+                       use_regs = insn_1a[20] /* L */ ? 0 : idxbit(rd);

                        def_cpsr = 0;
                        def_cpsr = 0;

-                       def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
+                       def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0;

                end
                `DECODE_SWI:    /* SWI */
                begin
                end
                `DECODE_SWI:    /* SWI */
                begin


@@ -238,7 +238,7 @@ module Issue(
        /* Condition checking logic */
        reg condition_met;
        always @(*)
        /* Condition checking logic */
        reg condition_met;
        always @(*)

-               casez(insn[31:28])
+               casez(insn_1a[31:28])

                `COND_EQ:       condition_met = cpsr[`CPSR_Z];
                `COND_NE:       condition_met = !cpsr[`CPSR_Z];
                `COND_CS:       condition_met = cpsr[`CPSR_C];
                `COND_EQ:       condition_met = cpsr[`CPSR_Z];
                `COND_NE:       condition_met = !cpsr[`CPSR_Z];
                `COND_CS:       condition_met = cpsr[`CPSR_C];


@@ -276,7 +276,7 @@ module Issue(
        wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
        wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
        wire waiting = waiting_cpsr | waiting_regs;
        wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
        wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
        wire waiting = waiting_cpsr | waiting_regs;

-       assign outstall = (waiting && !inbubble && !flush) || stall;
+       assign outstall = (waiting && !bubble_1a && !flush) || stall;

 
        reg delayedflush = 0;
        always @(posedge clk/* or negedge Nrst*/)
 
        reg delayedflush = 0;
        always @(posedge clk/* or negedge Nrst*/)


@@ -291,7 +291,7 @@ module Issue(
        always @(posedge clk or negedge Nrst)
        begin
                if (waiting)
        always @(posedge clk or negedge Nrst)
        begin
                if (waiting)

-                       $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
+                       $display("ISSUE: Stalling instruction %08x because %d/%d", insn_1a, waiting_cpsr, waiting_regs);

 
                if (!Nrst) begin
                        cpsr_inflight[0] <= 0;
 
                if (!Nrst) begin
                        cpsr_inflight[0] <= 0;


@@ -302,13 +302,13 @@ module Issue(
                end else if (!stall)
                begin
                        cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
                end else if (!stall)
                begin
                        cpsr_inflight[0] <= cpsr_inflight[1];   /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */

-                       cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
+                       cpsr_inflight[1] <= (waiting || bubble_1a || !condition_met) ? 0 : def_cpsr;

                        regs_inflight[0] <= regs_inflight[1];
                        regs_inflight[0] <= regs_inflight[1];

-                       regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
+                       regs_inflight[1] <= (waiting || bubble_1a || !condition_met) ? 0 : def_regs;

                        
                        

-                       outbubble <= inbubble | waiting | !condition_met | flush | delayedflush;
-                       outpc <= inpc;
-                       outinsn <= insn;
+                       outbubble <= bubble_1a | waiting | !condition_met | flush | delayedflush;
+                       outpc <= pc_1a;
+                       outinsn <= insn_1a;

                end
        end
 endmodule
                end
        end
 endmodule

diff --git a/RegFile.v b/RegFile.v
index 4ad48dd7f3202548acd56d02aa8c8e525bc544ce..836eae4090d1d2c8d5a1a7bb709ac447cb2d70d9 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,18 +1,18 @@
 module RegFile(
 module RegFile(

-       input clk,
-       input Nrst,
-       input [3:0] read_0,
-       output wire [31:0] rdata_0,
-       input [3:0] read_1,
-       output wire [31:0] rdata_1,
-       input [3:0] read_2,
-       output wire [31:0] rdata_2,
-       input [3:0] read_3,
-       output wire [31:0] rdata_3,
+       input              clk,
+       input              Nrst,
+       input        [3:0] rf__read_0_1a,
+       output wire [31:0] rf__rdata_0_1a,
+       input        [3:0] rf__read_1_1a,
+       output wire [31:0] rf__rdata_1_1a,
+       input        [3:0] rf__read_2_1a,
+       output wire [31:0] rf__rdata_2_1a,
+       input        [3:0] rf__read_3_4a,
+       output wire [31:0] rf__rdata_3_4a,

        output wire [31:0] spsr,
        output wire [31:0] spsr,

-       input write,
-       input [3:0] write_reg,
-       input [31:0] write_data
+       input              write,
+       input        [3:0] write_reg,
+       input       [31:0] write_data

        );
        
        reg [31:0] regfile [0:15];
        );
        
        reg [31:0] regfile [0:15];


@@ -23,10 +23,10 @@ module RegFile(
                        regfile[i] = 0;
        end
        
                        regfile[i] = 0;
        end
        

-       assign rdata_0 = ((read_0 == write_reg) && write) ? write_data : regfile[read_0];
-       assign rdata_1 = ((read_1 == write_reg) && write) ? write_data : regfile[read_1];
-       assign rdata_2 = ((read_2 == write_reg) && write) ? write_data : regfile[read_2];
-       assign rdata_3 = ((read_3 == write_reg) && write) ? write_data : regfile[read_3];
+       assign rf__rdata_0_1a = ((rf__read_0_1a == write_reg) && write) ? write_data : regfile[rf__read_0_1a];
+       assign rf__rdata_1_1a = ((rf__read_1_1a == write_reg) && write) ? write_data : regfile[rf__read_1_1a];
+       assign rf__rdata_2_1a = ((rf__read_2_1a == write_reg) && write) ? write_data : regfile[rf__read_2_1a];
+       assign rf__rdata_3_4a = ((rf__read_3_4a == write_reg) && write) ? write_data : regfile[rf__read_3_4a];

        assign spsr = regfile[4'hF];
        
        always @(posedge clk or negedge Nrst)
        assign spsr = regfile[4'hF];
        
        always @(posedge clk or negedge Nrst)

diff --git a/system.v b/system.v
index 1a5edfe94706439dc5b4e4a8fad027dc62cae081..433687f9bc34f2e00293366741263c88dfd80e68 100644 (file)
--- a/system.v
+++ b/system.v
@@ -111,12 +111,24 @@ module System(input clk, input rst
        wire [31:0] pc_out_execute;
        wire [31:0] pc_out_memory;
        
        wire [31:0] pc_out_execute;
        wire [31:0] pc_out_memory;
        

+       wire Nrst = ~rst;
+       

        /*AUTOWIRE*/
        // Beginning of automatic wires (for undeclared instantiated-module outputs)
        /*AUTOWIRE*/
        // Beginning of automatic wires (for undeclared instantiated-module outputs)

+       wire            bubble_1a;              // From fetch of Fetch.v

        wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
        wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
        wire            ic__rd_req_0a;          // From fetch of Fetch.v
        wire            ic__rd_wait_0a;         // From icache of ICache.v
        wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
        wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
        wire            ic__rd_req_0a;          // From fetch of Fetch.v
        wire            ic__rd_wait_0a;         // From icache of ICache.v

+       wire [31:0]     insn_1a;                // From fetch of Fetch.v
+       wire [31:0]     pc_1a;                  // From fetch of Fetch.v
+       wire [31:0]     rf__rdata_0_1a;         // From regfile of RegFile.v
+       wire [31:0]     rf__rdata_1_1a;         // From regfile of RegFile.v
+       wire [31:0]     rf__rdata_2_1a;         // From regfile of RegFile.v
+       wire [31:0]     rf__rdata_3_4a;         // From regfile of RegFile.v
+       wire [3:0]      rf__read_0_1a;          // From decode of Decode.v
+       wire [3:0]      rf__read_1_1a;          // From decode of Decode.v
+       wire [3:0]      rf__read_2_1a;          // From decode of Decode.v

        // End of automatics
 
        wire execute_out_backflush;
        // End of automatics
 
        wire execute_out_backflush;


@@ -174,14 +186,9 @@ module System(input clk, input rst
                .bus_ready(bus_ready_blockram));
 
        /* Fetch AUTO_TEMPLATE (
                .bus_ready(bus_ready_blockram));
 
        /* Fetch AUTO_TEMPLATE (

-               .clk(clk),
-               .Nrst(~rst),

                .stall_0a(stall_cause_issue),
                .jmp_0a(jmp),
                .jmppc_0a(jmppc),
                .stall_0a(stall_cause_issue),
                .jmp_0a(jmp),
                .jmppc_0a(jmppc),

-               .bubble_1a(bubble_out_fetch),
-               .insn_1a(insn_out_fetch),
-               .pc_1a(pc_out_fetch),

                );
        */
        Fetch fetch(
                );
        */
        Fetch fetch(


@@ -189,42 +196,106 @@ module System(input clk, input rst
                    // Outputs
                    .ic__rd_addr_0a     (ic__rd_addr_0a[31:0]),
                    .ic__rd_req_0a      (ic__rd_req_0a),
                    // Outputs
                    .ic__rd_addr_0a     (ic__rd_addr_0a[31:0]),
                    .ic__rd_req_0a      (ic__rd_req_0a),

-                   .bubble_1a          (bubble_out_fetch),      // Templated
-                   .insn_1a            (insn_out_fetch),        // Templated
-                   .pc_1a              (pc_out_fetch),          // Templated
+                   .bubble_1a          (bubble_1a),
+                   .insn_1a            (insn_1a[31:0]),
+                   .pc_1a              (pc_1a[31:0]),

                    // Inputs
                    // Inputs

-                   .clk                (clk),                   // Templated
-                   .Nrst               (~rst),                  // Templated
+                   .clk                (clk),
+                   .Nrst               (Nrst),

                    .ic__rd_wait_0a     (ic__rd_wait_0a),
                    .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
                    .stall_0a           (stall_cause_issue),     // Templated
                    .jmp_0a             (jmp),                   // Templated
                    .jmppc_0a           (jmppc));                // Templated
        
                    .ic__rd_wait_0a     (ic__rd_wait_0a),
                    .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
                    .stall_0a           (stall_cause_issue),     // Templated
                    .jmp_0a             (jmp),                   // Templated
                    .jmppc_0a           (jmppc));                // Templated
        

+       /* Issue AUTO_TEMPLATE (
+               .stall(stall_cause_execute),
+               .flush(execute_out_backflush | writeback_out_backflush),
+               .cpsr(writeback_out_cpsr),
+               .outstall(stall_cause_issue),
+               .outbubble(bubble_out_issue),
+               .outpc(pc_out_issue),
+               .outinsn(insn_out_issue),
+               );
+       */

        Issue issue(
        Issue issue(

-               .clk(clk),
-               .Nrst(~rst),
-               .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
-               .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
-               .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
-               .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
-               .outpc(pc_out_issue), .outinsn(insn_out_issue));
+               /*AUTOINST*/
+                   // Outputs
+                   .outstall           (stall_cause_issue),     // Templated
+                   .outbubble          (bubble_out_issue),      // Templated
+                   .outpc              (pc_out_issue),          // Templated
+                   .outinsn            (insn_out_issue),        // Templated
+                   // Inputs
+                   .clk                (clk),
+                   .Nrst               (Nrst),
+                   .stall              (stall_cause_execute),   // Templated
+                   .flush              (execute_out_backflush | writeback_out_backflush), // Templated
+                   .bubble_1a          (bubble_1a),
+                   .insn_1a            (insn_1a[31:0]),
+                   .pc_1a              (pc_1a[31:0]),
+                   .cpsr               (writeback_out_cpsr));   // Templated

        
        

-       RegFile regfile(
-               .clk(clk), .Nrst(~rst),
-               .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
-               .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
+       /* RegFile AUTO_TEMPLATE (

                .spsr(regfile_spsr),
                .spsr(regfile_spsr),

-               .write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
+               .write(regfile_write),
+               .write_reg(regfile_write_reg),
+               .write_data(regfile_write_data),
+               );
+       */
+       wire [3:0] rf__read_3_4a;
+       RegFile regfile(
+               /*AUTOINST*/
+                       // Outputs
+                       .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
+                       .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
+                       .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
+                       .rf__rdata_3_4a (rf__rdata_3_4a[31:0]),
+                       .spsr           (regfile_spsr),          // Templated
+                       // Inputs
+                       .clk            (clk),
+                       .Nrst           (Nrst),
+                       .rf__read_0_1a  (rf__read_0_1a[3:0]),
+                       .rf__read_1_1a  (rf__read_1_1a[3:0]),
+                       .rf__read_2_1a  (rf__read_2_1a[3:0]),
+                       .rf__read_3_4a  (rf__read_3_4a[3:0]),
+                       .write          (regfile_write),         // Templated
+                       .write_reg      (regfile_write_reg),     // Templated
+                       .write_data     (regfile_write_data));   // Templated

        
        

-       Decode decode(
-               .clk(clk),
+       /* Decode AUTO_TEMPLATE (

                .stall(stall_cause_execute),
                .stall(stall_cause_execute),

-               .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
-               .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
-               .carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
-               .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
-               .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
+               .incpsr(writeback_out_cpsr),
+               .inspsr(writeback_out_spsr),
+               .op0(decode_out_op0),
+               .op1(decode_out_op1),
+               .op2(decode_out_op2),
+               .carry(decode_out_carry),
+               .outcpsr(decode_out_cpsr),
+               .outspsr(decode_out_spsr),
+               );
+       */
+       Decode decode(
+               /*AUTOINST*/
+                     // Outputs
+                     .op0              (decode_out_op0),        // Templated
+                     .op1              (decode_out_op1),        // Templated
+                     .op2              (decode_out_op2),        // Templated
+                     .carry            (decode_out_carry),      // Templated
+                     .outcpsr          (decode_out_cpsr),       // Templated
+                     .outspsr          (decode_out_spsr),       // Templated
+                     .rf__read_0_1a    (rf__read_0_1a[3:0]),
+                     .rf__read_1_1a    (rf__read_1_1a[3:0]),
+                     .rf__read_2_1a    (rf__read_2_1a[3:0]),
+                     // Inputs
+                     .clk              (clk),
+                     .stall            (stall_cause_execute),   // Templated
+                     .insn_1a          (insn_1a[31:0]),
+                     .pc_1a            (pc_1a[31:0]),
+                     .incpsr           (writeback_out_cpsr),    // Templated
+                     .inspsr           (writeback_out_spsr),    // Templated
+                     .rf__rdata_0_1a   (rf__rdata_0_1a[31:0]),
+                     .rf__rdata_1_1a   (rf__rdata_1_1a[31:0]),
+                     .rf__rdata_2_1a   (rf__rdata_2_1a[31:0]));

        
        Execute execute(
                .clk(clk), .Nrst(~rst),
        
        Execute execute(
                .clk(clk), .Nrst(~rst),


@@ -247,7 +318,7 @@ module System(input clk, input rst
                /* stall? */ .flush(writeback_out_backflush),
                .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
                .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
                /* stall? */ .flush(writeback_out_backflush),
                .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
                .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),

-               .st_read(regfile_read_3), .st_data(regfile_rdata_3),
+               .st_read(rf__read_3_4a), .st_data(rf__rdata_3_4a),

                .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
                .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
                .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
                .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
                .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
                .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),


@@ -284,7 +355,7 @@ module System(input clk, input rst
        begin
                clockno <= clockno + 1;
                $display("------------------------------------------------------------------------------");
        begin
                clockno <= clockno + 1;
                $display("------------------------------------------------------------------------------");

-               $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
+               $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);

                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
                $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
                $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
                $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
                $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);