Add a BigBlockRAM that's 8MB (and obviously not very synthesizable). Make system...
[firearm.git] / system.v
1 `define BUS_ICACHE 1
2 `define BUS_DCACHE 0
3
4 module System(input clk);
5         wire [7:0] bus_req;
6         wire [7:0] bus_ack;
7         wire [31:0] bus_addr;
8         wire [31:0] bus_rdata;
9         wire [31:0] bus_wdata;
10         wire bus_rd, bus_wr;
11         wire bus_ready;
12
13         wire bus_req_icache;
14         wire bus_req_dcache;
15         assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
16         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
17         wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
18         
19         wire [31:0] bus_addr_icache;
20         wire [31:0] bus_wdata_icache;
21         wire bus_rd_icache;
22         wire bus_wr_icache;
23         
24         wire [31:0] bus_addr_dcache;
25         wire [31:0] bus_wdata_dcache;
26         wire bus_rd_dcache;
27         wire bus_wr_dcache;
28         
29         wire [31:0] bus_rdata_blockram;
30         wire bus_ready_blockram;
31         
32         assign bus_addr = bus_addr_icache | bus_addr_dcache;
33         assign bus_rdata = bus_rdata_blockram;
34         assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
35         assign bus_rd = bus_rd_icache | bus_rd_dcache;
36         assign bus_wr = bus_wr_icache | bus_wr_dcache;
37         assign bus_ready = bus_ready_blockram;
38
39         wire [31:0] icache_rd_addr;
40         wire icache_rd_req;
41         wire icache_rd_wait;
42         wire [31:0] icache_rd_data;
43         
44         wire [31:0] dcache_addr;
45         wire dcache_rd_req, dcache_wr_req;
46         wire dcache_rw_wait;
47         wire [31:0] dcache_wr_data, dcache_rd_data;
48         
49         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
50         wire decode_out_carry;
51         
52         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
53         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
54         wire regfile_write;
55         wire [3:0] regfile_write_reg;
56         wire [31:0] regfile_write_data;
57         
58         wire execute_out_write_reg;
59         wire [3:0] execute_out_write_num;
60         wire [31:0] execute_out_write_data;
61         wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
62         wire [31:0] execute_out_cpsr, execute_out_spsr;
63         wire execute_out_cpsrup;
64         
65         wire jmp_out_execute, jmp_out_writeback;
66         wire [31:0] jmppc_out_execute, jmppc_out_writeback;
67         wire jmp = jmp_out_execute | jmp_out_writeback;
68         wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
69         
70         wire memory_out_write_reg;
71         wire [3:0] memory_out_write_num;
72         wire [31:0] memory_out_write_data;
73         wire [31:0] memory_out_cpsr, memory_out_spsr;
74         wire memory_out_cpsrup;
75         
76         wire [31:0] writeback_out_cpsr, writeback_out_spsr;
77
78         wire cp_ack_terminal;
79         wire cp_busy_terminal;
80         wire [31:0] cp_read_terminal;
81         
82         wire cp_req;
83         wire [31:0] cp_insn;
84         wire cp_ack = cp_ack_terminal;
85         wire cp_busy = cp_busy_terminal;
86         wire cp_rnw;
87         wire [31:0] cp_read = cp_read_terminal;
88         wire [31:0] cp_write;
89         
90         wire stall_cause_issue;
91         wire stall_cause_execute;
92         wire stall_cause_memory;
93         wire bubble_out_fetch;
94         wire bubble_out_issue;
95         wire bubble_out_execute;
96         wire bubble_out_memory;
97         wire [31:0] insn_out_fetch;
98         wire [31:0] insn_out_issue;
99         wire [31:0] insn_out_execute;
100         wire [31:0] insn_out_memory;
101         wire [31:0] pc_out_fetch;
102         wire [31:0] pc_out_issue;
103         wire [31:0] pc_out_execute;
104         wire [31:0] pc_out_memory;
105
106         wire execute_out_backflush;
107         wire writeback_out_backflush;
108
109         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
110
111         ICache icache(
112                 .clk(clk),
113                 /* XXX reset? */
114                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
115                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
116                 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
117                 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
118                 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
119                 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
120         
121         DCache dcache(
122                 .clk(clk),
123                 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
124                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
125                 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
126                 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
127                 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
128                 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
129
130 `ifdef verilator
131         BigBlockRAM
132 `else
133         BlockRAM
134 `endif
135         blockram(
136                 .clk(clk),
137                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
138                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
139                 .bus_ready(bus_ready_blockram));
140
141         Fetch fetch(
142                 .clk(clk),
143                 .Nrst(1'b1 /* XXX */),
144                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
145                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
146                 .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
147                 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
148                 .pc(pc_out_fetch));
149         
150         Issue issue(
151                 .clk(clk),
152                 .Nrst(1'b1 /* XXX */),
153                 .stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
154                 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
155                 .inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
156                 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
157                 .outpc(pc_out_issue), .outinsn(insn_out_issue));
158         
159         RegFile regfile(
160                 .clk(clk),
161                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
162                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
163                 .spsr(regfile_spsr),
164                 .write(regfile_write), .write_reg(regfile_write_reg), .write_data(regfile_write_data));
165         
166         Decode decode(
167                 .clk(clk),
168                 .stall(stall_cause_execute),
169                 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
170                 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
171                 .carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),
172                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
173                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
174         
175         Execute execute(
176                 .clk(clk), .Nrst(1'b0),
177                 .stall(stall_cause_memory), .flush(writeback_out_backflush),
178                 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
179                 .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
180                 .op2(decode_out_op2), .carry(decode_out_carry),
181                 .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
182                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
183                 .write_data(execute_out_write_data),
184                 .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
185                 .outpc(pc_out_execute), .outinsn(insn_out_execute),
186                 .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
187                 .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
188         assign execute_out_backflush = jmp;
189         
190         assign cp_insn = insn_out_execute;
191         Memory memory(
192                 .clk(clk), .Nrst(1'b0),
193                 /* stall? */ .flush(writeback_out_backflush),
194                 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
195                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
196                 .st_read(regfile_read_3), .st_data(regfile_rdata_3),
197                 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
198                 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
199                 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
200                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
201                 .outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
202                 .outpc(pc_out_memory), .outinsn(insn_out_memory),
203                 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
204                 .out_write_data(memory_out_write_data),
205                 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
206                 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
207         
208         Terminal terminal(      
209                 .clk(clk),
210                 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
211                 .cp_read(cp_read_terminal), .cp_write(cp_write));
212         
213         Writeback writeback(
214                 .clk(clk),
215                 .inbubble(bubble_out_memory),
216                 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
217                 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
218                 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
219                 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
220                 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
221         assign writeback_out_backflush = jmp_out_writeback;
222
223         reg [31:0] clockno = 0;
224         always @(posedge clk)
225         begin
226                 clockno <= clockno + 1;
227                 $display("------------------------------------------------------------------------------");
228                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
229                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
230                 $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
231                 $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
232                 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
233                 $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
234         end
235 endmodule
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