Memory: Fix up latch logic for LDM/STM.

diff --git a/Memory.v b/Memory.v
index 985541148a766ac8e12c7920e8a9cc3025763bab..b7710b0aae5aac3a78e418be7530fc77f197878d 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -583,7 +583,7 @@ module Memory(
        
        /* LDM/STM register control logic. */
        always @(posedge clk)
-               if (!rw_wait)
+               if (!rw_wait || lsm_state != `LSM_MEMIO)
                begin
                        prev_reg <= cur_reg;
                        regs <= next_regs;