ICache and DCache: Do not accept fill data if the bus_ready is actually intended...

diff --git a/DCache.v b/DCache.v
index a3484a7558b81e5bf3db42a4d11e3b0f2b834e5b..edfcde194daa200d5b030da7825c6d7745b75423 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -79,7 +79,7 @@ module DCache(
                if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))        /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
                        cache_fill_pos <= 0;
                else if (rd_req && !cache_hit) begin
-                       if (bus_ready) begin    /* Started the fill, and we have data. */
+                       if (bus_ready && bus_ack) begin /* Started the fill, and we have data. */
                                cache_data[idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */

diff --git a/ICache.v b/ICache.v
index 8106259ef9a175a417ab22ccbe849f1b02d7deef..b9e4eff39415b0569b866ebf159f4609f30304e9 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -70,7 +70,7 @@ module ICache(
                if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))      /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
                        cache_fill_pos <= 0;
                else if (rd_req && !cache_hit) begin
-                       if (bus_ready) begin    /* Started the fill, and we have data. */
+                       if (bus_ack && bus_ready) begin /* Started the fill, and we have data. */
                                $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
                                cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;