Fix a few scattered bugs, and get fetch to work.

diff --git a/blockram.v b/BlockRAM.v
similarity index 78%
rename from blockram.v
rename to BlockRAM.v
index fd36875ba12f1ef44ad4e5dd080774e882b402fa..85f865974fbd3f3bb88e13bb2d3cfe274d0b3607 100644 (file)
--- a/blockram.v
+++ b/BlockRAM.v
@@ -12,9 +12,11 @@ module BlockRAM(
         * 0x00004000.  rdata and ready must be driven to zero if the
         * address is not within the range of this module.
         */
         * 0x00004000.  rdata and ready must be driven to zero if the
         * address is not within the range of this module.
         */

-       wire decode = (addr & ~32'h00003FFF) == 32'h00004000;
-       wire [13:2] ramaddr = addr & 14'h3FFC;  /* mask off lower two bits
-                                                * for word alignment */
+       wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
+       /* verilator lint_off WIDTH */
+       wire [13:2] ramaddr = bus_addr & 32'h3FFC;      /* mask off lower two bits
+                                                        * for word alignment */
+       /* verilator lint_on WIDTH */

        
        reg [31:0] data [0:(16384 / 4 - 1)];
        
        
        reg [31:0] data [0:(16384 / 4 - 1)];
        

diff --git a/BusArbiter.v b/BusArbiter.v
new file mode 100644 (file)
index 0000000..2ddea59
--- /dev/null
+++ b/BusArbiter.v
@@ -0,0 +1,17 @@
+module BusArbiter(
+       input [7:0] bus_req,
+       output reg [7:0] bus_ack);
+
+       always @(*)
+               casez (bus_req)
+               8'b00000000: bus_ack = 8'b00000000;
+               8'b???????1: bus_ack = 8'b00000001;
+               8'b??????10: bus_ack = 8'b00000010;
+               8'b?????100: bus_ack = 8'b00000100;
+               8'b????1000: bus_ack = 8'b00001000;
+               8'b???10000: bus_ack = 8'b00010000;
+               8'b??100000: bus_ack = 8'b00100000;
+               8'b?1000000: bus_ack = 8'b01000000;
+               8'b10000000: bus_ack = 8'b10000000;
+               endcase
+endmodule

diff --git a/fetch.v b/Fetch.v
similarity index 68%
rename from fetch.v
rename to Fetch.v
index 885b29c579911f3d49a198195d0b4bef1f989fe6..0a18b31e6e9a4c68cc5b83112257e5ea58c1a7d2 100644 (file)
--- a/fetch.v
+++ b/Fetch.v
@@ -9,26 +9,26 @@ module Fetch(
        
        input stall,
        input jmp,
        
        input stall,
        input jmp,

-       input [31:0] jmppc;
+       input [31:0] jmppc,

        output wire bubble,
        output wire [31:0] insn,
        output reg [31:0] pc);
 
        reg [31:0] prevpc;
        initial
        output wire bubble,
        output wire [31:0] insn,
        output reg [31:0] pc);
 
        reg [31:0] prevpc;
        initial

-               prevpc <= 32'h0;
+               prevpc = 32'hFFFFFFFC;  /* ugh... the first pc we request will be this +4 */

        always @(negedge Nrst)
        always @(negedge Nrst)

-               prevpc <= 32'h0;
+               prevpc <= 32'hFFFFFFFC;

        
        always @(*)
                if (!Nrst)
        
        always @(*)
                if (!Nrst)

-                       pc <= 32'h0;
+                       pc = 32'hFFFFFFFC;

                else if (stall) /* don't change any internal state */
                else if (stall) /* don't change any internal state */

-                       pc <= prevpc;
+                       pc = prevpc;

                else if (jmp)
                else if (jmp)

-                       pc <= jmppc;
+                       pc = jmppc;

                else
                else

-                       pc <= prevpc + 32'h4;
+                       pc = prevpc + 32'h4;

        
        assign bubble = stall | rd_wait;
        assign rd_addr = pc;
        
        assign bubble = stall | rd_wait;
        assign rd_addr = pc;


@@ -36,5 +36,6 @@ module Fetch(
        assign insn = rd_data;
                        
        always @(posedge clk)
        assign insn = rd_data;
                        
        always @(posedge clk)

-               prevpc <= pc;
+               if (!rd_wait || !Nrst)
+                       prevpc <= pc;

 endmodule
 endmodule

diff --git a/icache.v b/ICache.v
similarity index 82%
rename from icache.v
rename to ICache.v
index 3dd9cc3c9117e03b128cd151eda4a3c7b986c138..3a9f14481be7a2cc9c92dcbd036d7193602cf9ae 100644 (file)
--- a/icache.v
+++ b/ICache.v
@@ -50,15 +50,12 @@ module ICache(
        end
        
        reg [3:0] cache_fill_pos = 0;
        end
        
        reg [3:0] cache_fill_pos = 0;

+       assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */

        always @(*)
        always @(*)

-               if (rd_req && !cache_hit) begin
-                       bus_req = 1;
-                       if (bus_ack) begin
-                               bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
-                               bus_rd = 1;
-                       end
+               if (rd_req && !cache_hit && bus_ack) begin
+                       bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
+                       bus_rd = 1;

                end else begin
                end else begin

-                       bus_req = 0;

                        bus_addr = 0;
                        bus_rd = 0;
                end
                        bus_addr = 0;
                        bus_rd = 0;
                end


@@ -66,11 +63,11 @@ module ICache(
        always @(posedge clk)
                if (rd_req && !cache_hit) begin
                        if (bus_ready) begin    /* Started the fill, and we have data. */
        always @(posedge clk)
                if (rd_req && !cache_hit) begin
                        if (bus_ready) begin    /* Started the fill, and we have data. */

-                               cache_data[rd_idx][cache_fill_pos] = bus_data;
+                               cache_data[rd_idx][cache_fill_pos] <= bus_rdata;

                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */
                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */

-                                       cache_tags[rd_idx] = rd_tag;
-                                       cache_valid[rd_idx] = 1;
+                                       cache_tags[rd_idx] <= rd_tag;
+                                       cache_valid[rd_idx] <= 1;

                                end
                        end
                end
                                end
                        end
                end

diff --git a/busarb.v b/busarb.v
deleted file mode 100644 (file)
index 05a5130..0000000
--- a/busarb.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module BusArbiter(
-       input [7:0] bus_req,
-       output reg [7:0] bus_ack);
-
-       always @(*)
-               casex (bus_req)
-               8'b00000000: bus_ack <= 8'b00000000;
-               8'bxxxxxxx1: bus_ack <= 8'b00000001;
-               8'bxxxxxx10: bus_ack <= 8'b00000010;
-               8'bxxxxx100: bus_ack <= 8'b00000100;
-               8'bxxxx1000: bus_ack <= 8'b00001000;
-               8'bxxx10000: bus_ack <= 8'b00010000;
-               8'bxx100000: bus_ack <= 8'b00100000;
-               8'bx1000000: bus_ack <= 8'b01000000;
-               8'b10000000: bus_ack <= 8'b10000000;
-               endcase
-endmodule

diff --git a/system.v b/system.v
index 1035489c237ac9185a351dd18e81d9a4c0418bef..0c25de3a9e3f28b6fb13212fb16fc762cf5ba39e 100644 (file)
--- a/system.v
+++ b/system.v
@@ -8,9 +8,11 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
        wire [31:0] bus_wdata;
        wire bus_rd, bus_wr;
        wire bus_ready;
        wire [31:0] bus_wdata;
        wire bus_rd, bus_wr;
        wire bus_ready;

-       
-       wire bus_req_icache = bus_req[`BUS_ICACHE];
+
+       wire bus_req_icache;    
+       assign bus_req = {7'b0, bus_req_icache};

        wire bus_ack_icache = bus_ack[`BUS_ICACHE];
        wire bus_ack_icache = bus_ack[`BUS_ICACHE];

+       

        wire [31:0] bus_addr_icache;
        wire [31:0] bus_wdata_icache;
        wire bus_rd_icache;
        wire [31:0] bus_addr_icache;
        wire [31:0] bus_wdata_icache;
        wire bus_rd_icache;


@@ -42,7 +44,7 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
                .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
                .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
                .bus_wr(bus_wr_icache), .bus_ready(bus_ready));

-
+       

        BlockRAM blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
        BlockRAM blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),