Wire the fetch unit into the top module

diff --git a/system.v b/system.v
index ebf0882701fa91b275cb64ef0f28c5e59fcc2099..1035489c237ac9185a351dd18e81d9a4c0418bef 100644 (file)
--- a/system.v
+++ b/system.v
@@ -1,6 +1,6 @@
 `define BUS_ICACHE 0
 
 `define BUS_ICACHE 0
 

-module System(input clk);
+module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);

        wire [7:0] bus_req;
        wire [7:0] bus_ack;
        wire [31:0] bus_addr;
        wire [7:0] bus_req;
        wire [7:0] bus_ack;
        wire [31:0] bus_addr;


@@ -25,12 +25,19 @@ module System(input clk);
        assign bus_rd = bus_rd_icache;
        assign bus_wr = bus_wr_icache;
        assign bus_ready = bus_ready_blockram;
        assign bus_rd = bus_rd_icache;
        assign bus_wr = bus_wr_icache;
        assign bus_ready = bus_ready_blockram;

+       
+       wire [31:0] icache_rd_addr;
+       wire icache_rd_req;
+       wire icache_rd_wait;
+       wire [31:0] icache_rd_data;

 
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
        ICache icache(
                .clk(clk),
 
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
        ICache icache(
                .clk(clk),

-               .rd_addr(), .rd_req(), .rd_wait(), .rd_data(),
+               /* XXX reset? */
+               .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
+               .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),

                .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
                .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
                .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
                .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),


@@ -42,4 +49,12 @@ module System(input clk);
                .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
                .bus_ready(bus_ready_blockram));
 
                .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
                .bus_ready(bus_ready_blockram));
 

+       Fetch fetch(
+               .clk(clk),
+               .Nrst(1 /* XXX */),
+               .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
+               .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
+               .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
+               .bubble(bubbleshield), .insn(insn), .pc(pc));
+

 endmodule
 endmodule