Return decode to a state of cleanliness.

diff --git a/Decode.v b/Decode.v
index fd8554bb8ecde600d59e8256dc1dff7029963106..42ae993020203e08b3b908acbdddc40930bab1bd 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -8,7 +8,7 @@ module Decode(
        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,

-       output reg [31:0] outcpsr,
+       output reg carry,

 
        output [3:0] read_0,
        output [3:0] read_1,
 
        output [3:0] read_0,
        output [3:0] read_1,


@@ -19,7 +19,8 @@ module Decode(
        );
 
        wire [31:0] regs0, regs1, regs2, rpc;
        );
 
        wire [31:0] regs0, regs1, regs2, rpc;

-       wire [31:0] op1_res, cpsr;
+       wire [31:0] op0_out, op1_out, op2_out;
+       wire carry_out;

 
        /* shifter stuff */
        wire [31:0] shift_oper;
 
        /* shifter stuff */
        wire [31:0] shift_oper;


@@ -79,10 +80,11 @@ module Decode(
 //                     read_0 = insn[11:8]; /* Rn */
 //                     read_1 = insn[3:0];   /* Rm */
 //                     read_2 = 4'b0;       /* anyus */
 //                     read_0 = insn[11:8]; /* Rn */
 //                     read_1 = insn[3:0];   /* Rm */
 //                     read_2 = 4'b0;       /* anyus */

-               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
+               begin end

                32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
                32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
                32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
                32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */

-               begin end       /* Everything stays x'ed out. */
+                       read_0 = insn[3:0];     /* Rm */

                32'b????00??????????????????????????:   /* ALU */
                begin
                        read_0 = insn[19:16]; /* Rn */
                32'b????00??????????????????????????:   /* ALU */
                begin
                        read_0 = insn[19:16]; /* Rn */


@@ -104,7 +106,6 @@ module Decode(
                32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];
                32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];

-                       read_1 = insn[3:0];

                end
                32'b????011????????????????????1????:   /* Undefined. I hate ARM */
                begin end
                end
                32'b????011????????????????????1????:   /* Undefined. I hate ARM */
                begin end


@@ -119,8 +120,10 @@ module Decode(
                begin end
                32'b????110?????????????????????????:   /* Coprocessor data transfer */
                        read_0 = insn[19:16];
                begin end
                32'b????110?????????????????????????:   /* Coprocessor data transfer */
                        read_0 = insn[19:16];

-               32'b????1110???????????????????0????,   /* Coprocessor data op */
-               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1110???????????????????0????:   /* Coprocessor data op */
+               begin end
+               32'b????1110???????????????????1????:   /* Coprocessor register transfer */
+                       read_0 = insn[15:12];

                32'b????1111????????????????????????:   /* SWI */
                begin end
                default:
                32'b????1111????????????????????????:   /* SWI */
                begin end
                default:


@@ -129,90 +132,96 @@ module Decode(
        end
        
        always @(*) begin
        end
        
        always @(*) begin

-               op1_res = 32'hxxxxxxxx;
-               cpsr = 32'hxxxxxxxx;
+               op0_out = 32'hxxxxxxxx;
+               op1_out = 32'hxxxxxxxx;
+               op2_out = 32'hxxxxxxxx;
+               carry_out = 1'bx;

                casez (insn)
                32'b????000000??????????????1001????: begin /* Multiply */
                casez (insn)
                32'b????000000??????????????1001????: begin /* Multiply */

-                       op1_res = regs1;
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = regs1;
+                       op2_out = regs2;

                end
 //             32'b????00001???????????????1001????: begin /* Multiply long */
 //                     op1_res = regs1;
 //             end
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
                end
 //             32'b????00001???????????????1001????: begin /* Multiply long */
 //                     op1_res = regs1;
 //             end
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */

-                       cpsr = incpsr;

                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */

-                       cpsr = incpsr;
+                       op0_out = regs0;

                end
                end

-                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
-                       cpsr = incpsr;
+                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       if(insn[25]) begin     /* the constant case */
+                               op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
+                       end else begin
+                               op0_out = regs0;
+                       end

                 end
                32'b????00??????????????????????????: begin /* ALU */
                 end
                32'b????00??????????????????????????: begin /* ALU */

+                       op0_out = regs0;

                        if(insn[25]) begin     /* the constant case */
                        if(insn[25]) begin     /* the constant case */

-                               cpsr = incpsr;
-                               op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
+                               carry_out = incpsr[`CPSR_C];
+                               op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));

                        end else begin
                        end else begin

-                               cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
-                               op1_res = shift_res;
+                               carry_out = shift_cflag_out;
+                               op1_out = shift_res;

                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */

-                       op1_res = regs1;
+                       op0_out = regs0;
+                       op1_out = regs1;

                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */

-                       cpsr = incpsr;
+                       op0_out = regs0;

                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */

-                       op1_res = regs1;
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = regs1;

                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */

-                       op1_res = {24'b0, insn[11:8], insn[3:0]};
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = {24'b0, insn[11:8], insn[3:0]};

                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */
                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */

+                       op0_out = regs0;

                        if(insn[25]) begin
                        if(insn[25]) begin

-                               op1_res = {20'b0, insn[11:0]};
-                               cpsr = incpsr;
+                               op1_out = {20'b0, insn[11:0]};
+                               carry_out = incpsr[`CPSR_C];

                        end else begin
                        end else begin

-                               op1_res = shift_res;
-                               cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
+                               op1_out = shift_res;
+                               carry_out = shift_cflag_out;

                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */
                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */

-                       op1_res = {16'b0, insn[15:0]};
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = {16'b0, insn[15:0]};

                end
                32'b????101?????????????????????????: begin /* Branch */
                end
                32'b????101?????????????????????????: begin /* Branch */

-                       op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
-                       cpsr = incpsr;
+                       op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};

                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */

-                       op1_res = {24'b0, insn[7:0]};
-                       cpsr = incpsr;
+                       op0_out = regs0;
+                       op1_out = {24'b0, insn[7:0]};

                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */
                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */

-                       cpsr = incpsr;

                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */

-                       cpsr = incpsr;
+                       op0_out = regs0;

                end
                32'b????1111????????????????????????: begin /* SWI */
                end
                32'b????1111????????????????????????: begin /* SWI */

-                       cpsr = incpsr;

                end
                default: begin end
                endcase
        end
 
        always @ (posedge clk) begin
                end
                default: begin end
                endcase
        end
 
        always @ (posedge clk) begin

-               op0 <= regs0;   /* Rn - always */
-               op1 <= op1_res; /* 'operand 2' - Rm */
-               op2 <= regs2;   /* thirdedge - Rs */
-               outcpsr <= cpsr;
+               op0 <= op0_out;   /* Rn - always */
+               op1 <= op1_out; /* 'operand 2' - Rm */
+               op2 <= op2_out;   /* thirdedge - Rs */
+               carry <= carry_out;

        end
 
 endmodule
        end
 
 endmodule

diff --git a/system.v b/system.v
index 251b43c348dd3d84e8ff14553e0ea2266014f563..fb28c4f47bead83b42e5cc8c38ce3436cbe4e2a7 100644 (file)
--- a/system.v
+++ b/system.v
@@ -38,7 +38,8 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
        wire stall_in_fetch = stall_cause_issue;
        wire stall_in_issue = 0;
        
        wire stall_in_fetch = stall_cause_issue;
        wire stall_in_issue = 0;
        

-       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr;
+       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2;
+       wire decode_out_carry;

        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
        wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
        
        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
        wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
        


@@ -99,7 +100,7 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .clk(clk),
                .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */),
                .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
                .clk(clk),
                .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */),
                .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),

-               .outcpsr(decode_out_cpsr),
+               .carry(decode_out_carry),

                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        


@@ -110,6 +111,6 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                $display("------------------------------------------------------------------------------");
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
                $display("------------------------------------------------------------------------------");
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);

-               $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, cpsr %08x", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr);
+               $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);

        end
 endmodule
        end
 endmodule