Return decode to a state of cleanliness.
[firearm.git] / system.v
1 `define BUS_ICACHE 0
2
3 module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);
4         wire [7:0] bus_req;
5         wire [7:0] bus_ack;
6         wire [31:0] bus_addr;
7         wire [31:0] bus_rdata;
8         wire [31:0] bus_wdata;
9         wire bus_rd, bus_wr;
10         wire bus_ready;
11
12         wire bus_req_icache;    
13         assign bus_req = {7'b0, bus_req_icache};
14         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
15         
16         wire [31:0] bus_addr_icache;
17         wire [31:0] bus_wdata_icache;
18         wire bus_rd_icache;
19         wire bus_wr_icache;
20         
21         wire [31:0] bus_rdata_blockram;
22         wire bus_ready_blockram;
23         
24         assign bus_addr = bus_addr_icache;
25         assign bus_rdata = bus_rdata_blockram;
26         assign bus_wdata = bus_wdata_icache;
27         assign bus_rd = bus_rd_icache;
28         assign bus_wr = bus_wr_icache;
29         assign bus_ready = bus_ready_blockram;
30         
31         wire [31:0] icache_rd_addr;
32         wire icache_rd_req;
33         wire icache_rd_wait;
34         wire [31:0] icache_rd_data;
35         
36         wire stall_cause_issue;
37         
38         wire stall_in_fetch = stall_cause_issue;
39         wire stall_in_issue = 0;
40         
41         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2;
42         wire decode_out_carry;
43         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
44         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
45         
46         wire bubble_out_fetch;
47         wire bubble_out_issue;
48         wire [31:0] insn_out_fetch;
49         wire [31:0] insn_out_issue;
50         wire [31:0] pc_out_fetch;
51         wire [31:0] pc_out_issue;
52         
53         assign bubbleshield = bubble_out_issue;
54         assign insn = insn_out_issue;
55         assign pc = pc_out_issue;
56
57         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
58
59         ICache icache(
60                 .clk(clk),
61                 /* XXX reset? */
62                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
63                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
64                 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
65                 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
66                 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
67                 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
68         
69         BlockRAM blockram(
70                 .clk(clk),
71                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
72                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
73                 .bus_ready(bus_ready_blockram));
74
75         Fetch fetch(
76                 .clk(clk),
77                 .Nrst(1 /* XXX */),
78                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
79                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
80                 .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
81                 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
82                 .pc(pc_out_fetch));
83         
84         Issue issue(
85                 .clk(clk),
86                 .Nrst(1 /* XXX */),
87                 .stall(stall_in_issue), .flush(0 /* XXX */),
88                 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
89                 .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
90                 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
91                 .outpc(pc_out_issue), .outinsn(insn_out_issue));
92         
93         RegFile regfile(
94                 .clk(clk),
95                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
96                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
97                 .write(0), .write_req(0), .write_data(0 /* XXX */));
98         
99         Decode decode(
100                 .clk(clk),
101                 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */),
102                 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
103                 .carry(decode_out_carry),
104                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
105                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
106         
107         reg [31:0] clockno = 0;
108         always @(posedge clk)
109         begin
110                 clockno <= clockno + 1;
111                 $display("------------------------------------------------------------------------------");
112                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
113                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
114                 $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
115         end
116 endmodule
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