RegFile: I/O rename

diff --git a/RegFile.v b/RegFile.v
index 836eae4090d1d2c8d5a1a7bb709ac447cb2d70d9..dec190757ceaf6a1c64e678ad8a440b3018efcb9 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -7,8 +7,8 @@ module RegFile(
        output wire [31:0] rf__rdata_1_1a,
        input        [3:0] rf__read_2_1a,
        output wire [31:0] rf__rdata_2_1a,
-       input        [3:0] rf__read_3_4a,
-       output wire [31:0] rf__rdata_3_4a,
+       input        [3:0] rf__read_3_3a,
+       output wire [31:0] rf__rdata_3_3a,
        output wire [31:0] spsr,
        input              write,
        input        [3:0] write_reg,
@@ -26,7 +26,7 @@ module RegFile(
        assign rf__rdata_0_1a = ((rf__read_0_1a == write_reg) && write) ? write_data : regfile[rf__read_0_1a];
        assign rf__rdata_1_1a = ((rf__read_1_1a == write_reg) && write) ? write_data : regfile[rf__read_1_1a];
        assign rf__rdata_2_1a = ((rf__read_2_1a == write_reg) && write) ? write_data : regfile[rf__read_2_1a];
-       assign rf__rdata_3_4a = ((rf__read_3_4a == write_reg) && write) ? write_data : regfile[rf__read_3_4a];
+       assign rf__rdata_3_3a = ((rf__read_3_3a == write_reg) && write) ? write_data : regfile[rf__read_3_3a];
        assign spsr = regfile[4'hF];
        
        always @(posedge clk or negedge Nrst)