From 0d897066e759e22608618b2cfba20fc09d08f1c3 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Thu, 11 Mar 2010 05:56:52 -0500 Subject: [PATCH] RegFile: I/O rename --- RegFile.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/RegFile.v b/RegFile.v index 836eae4..dec1907 100644 --- a/RegFile.v +++ b/RegFile.v @@ -7,8 +7,8 @@ module RegFile( output wire [31:0] rf__rdata_1_1a, input [3:0] rf__read_2_1a, output wire [31:0] rf__rdata_2_1a, - input [3:0] rf__read_3_4a, - output wire [31:0] rf__rdata_3_4a, + input [3:0] rf__read_3_3a, + output wire [31:0] rf__rdata_3_3a, output wire [31:0] spsr, input write, input [3:0] write_reg, @@ -26,7 +26,7 @@ module RegFile( assign rf__rdata_0_1a = ((rf__read_0_1a == write_reg) && write) ? write_data : regfile[rf__read_0_1a]; assign rf__rdata_1_1a = ((rf__read_1_1a == write_reg) && write) ? write_data : regfile[rf__read_1_1a]; assign rf__rdata_2_1a = ((rf__read_2_1a == write_reg) && write) ? write_data : regfile[rf__read_2_1a]; - assign rf__rdata_3_4a = ((rf__read_3_4a == write_reg) && write) ? write_data : regfile[rf__read_3_4a]; + assign rf__rdata_3_3a = ((rf__read_3_3a == write_reg) && write) ? write_data : regfile[rf__read_3_3a]; assign spsr = regfile[4'hF]; always @(posedge clk or negedge Nrst) -- 2.39.2