assign read_0 out

diff --git a/Decode.v b/Decode.v
index 763efba444ca31e5149edb047f9d3445386547d4..506480d81de2934d28c551379263e46cdc140007 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -45,7 +45,7 @@ module Decode(
                32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
                32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
                32'b????00010?00????????00001001????,   /* Atomic swap */
-               32'b????000100101111111111110001????,   /* Branch */
+               32'b????000100101111111111110001????,   /* Branch and exchange */
                32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
                32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
                32'b????011????????????????????1????,   /* Undefined. I hate ARM */
@@ -63,23 +63,58 @@ module Decode(
                        rpc = 32'hxxxxxxxx;
                endcase
 
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+                       read_0 = insn[15:12]; /* Rn */
+//             32'b????00001???????????????1001????,   /* Multiply long */
+//                     read_0 = insn[11:8]; /* Rn */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       read_0 = 4'hx;
+               32'b????00??????????????????????????:   /* ALU */
+                       read_0 = insn[19:16]; /* Rn */
+               32'b????00010?00????????00001001????:   /* Atomic swap */
+                       read_0 = insn[19:16]; /* Rn */
+               32'b????000100101111111111110001????:   /* Branch and exchange */
+                       read_0 = insn[3:0];   /* Rn */
+               32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
+                       read_0 = insn[19:16];
+               32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
+                       read_0 = insn[19:16];
+               32'b????011????????????????????1????:   /* Undefined. I hate ARM */
+                       read_0 = 4'hx;
+               32'b????01??????????????????????????:   /* Single data transfer */
+                       read_0 = insn[19:16]; /* Rn */
+               32'b????100?????????????????????????:   /* Block data transfer */
+                       read_0 = insn[19:16];
+               32'b????101?????????????????????????:   /* Branch */
+                       read_0 = 4'hx;
+               32'b????110?????????????????????????:   /* Coprocessor data transfer */
+                       read_0 = insn[19:16];
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       read_0 = 4'hx;
+               default:
+                       read_0 = 4'hx;
+               endcase
+
        always @ (*) begin
                casez (insn)
                32'b????000000??????????????1001????: begin /* Multiply */
-                       read_0 = insn[15:12]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                        read_2 = insn[11:8];  /* Rs */
                        op1_res = regs1;
                        cpsr = incpsr;
                end
-/*
-               32'b????00001???????????????1001????: begin * Multiply long *
-                       read_0 = insn[11:8]; * Rn *
+/*             32'b????00001???????????????1001????: begin * Multiply long *
+                       
                        read_1 = insn[3:0];  * Rm *
                        read_2 = 4'b0;       * anyus *
                        op1_res = regs1;
-               end
-*/
+               end*/
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
                        cpsr = incpsr;
                end
@@ -90,7 +125,6 @@ module Decode(
                        cpsr = incpsr;
                 end
                32'b????00??????????????????????????: begin /* ALU */
-                       read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                        read_2 = insn[11:8];  /* Rs for shift */
                        if(insn[25]) begin     /* the constant case */
@@ -102,24 +136,21 @@ module Decode(
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */
-                       read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                        read_2 = 4'b0;        /* anyus */
                        op1_res = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */
-                       read_0 = insn[3:0];   /* Rn */
                        cpsr = incpsr;
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
-                       read_0 = insn[19:16];
                        read_1 = insn[3:0];
                        read_2 = 4'b0;
                        op1_res = regs1;
                        cpsr = incpsr;
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
-                       read_0 = insn[19:16];
+                       
                        read_1 = insn[3:0];
                        op1_res = {24'b0, insn[11:8], insn[3:0]};
                        cpsr = incpsr;
@@ -128,7 +159,6 @@ module Decode(
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */
-                       read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                        if(insn[25]) begin
                                op1_res = {20'b0, insn[11:0]};
@@ -139,7 +169,6 @@ module Decode(
                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */
-                       read_0 = insn[19:16];
                        op1_res = {16'b0, insn[15:0]};
                        cpsr = incpsr;
                end
@@ -148,7 +177,6 @@ module Decode(
                        cpsr = incpsr;
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */
-                       read_0 = insn[19:16];
                        op1_res = {24'b0, insn[7:0]};
                        cpsr = incpsr;
                end