assign read_0 out
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         output reg [31:0] op0,
9         output reg [31:0] op1,
10         output reg [31:0] op2,
11         output reg [31:0] outcpsr,
12
13         output [3:0] read_0,
14         output [3:0] read_1,
15         output [3:0] read_2,
16         input [31:0] rdata_0,
17         input [31:0] rdata_1,
18         input [31:0] rdata_2
19         );
20
21         wire [31:0] regs0, regs1, regs2, rpc;
22         wire [31:0] op1_res, cpsr;
23
24         /* shifter stuff */
25         wire [31:0] shift_oper;
26         wire [31:0] shift_res;
27         wire shift_cflag_out;
28
29         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
30         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
31         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
32
33         IHATEARMSHIFT blowme(.insn(insn),
34                              .operand(regs1),
35                              .reg_amt(regs2),
36                              .cflag_in(incpsr[`CPSR_C]),
37                              .res(shift_res),
38                              .cflag_out(shift_cflag_out));
39         
40         always @(*)
41                 casez (insn)
42                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
43 //              32'b????00001???????????????1001????,   /* Multiply long */
44                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
45                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
46                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
47                 32'b????00010?00????????00001001????,   /* Atomic swap */
48                 32'b????000100101111111111110001????,   /* Branch and exchange */
49                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
50                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
51                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
52                 32'b????01??????????????????????????,   /* Single data transfer */
53                 32'b????100?????????????????????????,   /* Block data transfer */
54                 32'b????101?????????????????????????,   /* Branch */
55                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
56                 32'b????1110???????????????????0????,   /* Coprocessor data op */
57                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
58                 32'b????1111????????????????????????:   /* SWI */
59                         rpc = inpc - 8;
60                 32'b????00??????????????????????????:   /* ALU */
61                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
62                 default:                                /* X everything else out */
63                         rpc = 32'hxxxxxxxx;
64                 endcase
65
66         always @(*)
67                 casez (insn)
68                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
69                         read_0 = insn[15:12]; /* Rn */
70 //              32'b????00001???????????????1001????,   /* Multiply long */
71 //                      read_0 = insn[11:8]; /* Rn */
72                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
73                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
74                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
75                         read_0 = 4'hx;
76                 32'b????00??????????????????????????:   /* ALU */
77                         read_0 = insn[19:16]; /* Rn */
78                 32'b????00010?00????????00001001????:   /* Atomic swap */
79                         read_0 = insn[19:16]; /* Rn */
80                 32'b????000100101111111111110001????:   /* Branch and exchange */
81                         read_0 = insn[3:0];   /* Rn */
82                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
83                         read_0 = insn[19:16];
84                 32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
85                         read_0 = insn[19:16];
86                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
87                         read_0 = 4'hx;
88                 32'b????01??????????????????????????:   /* Single data transfer */
89                         read_0 = insn[19:16]; /* Rn */
90                 32'b????100?????????????????????????:   /* Block data transfer */
91                         read_0 = insn[19:16];
92                 32'b????101?????????????????????????:   /* Branch */
93                         read_0 = 4'hx;
94                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
95                         read_0 = insn[19:16];
96                 32'b????1110???????????????????0????,   /* Coprocessor data op */
97                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
98                 32'b????1111????????????????????????:   /* SWI */
99                         read_0 = 4'hx;
100                 default:
101                         read_0 = 4'hx;
102                 endcase
103
104         always @ (*) begin
105                 casez (insn)
106                 32'b????000000??????????????1001????: begin /* Multiply */
107                         read_1 = insn[3:0];   /* Rm */
108                         read_2 = insn[11:8];  /* Rs */
109                         op1_res = regs1;
110                         cpsr = incpsr;
111                 end
112 /*              32'b????00001???????????????1001????: begin * Multiply long *
113                         
114                         read_1 = insn[3:0];  * Rm *
115                         read_2 = 4'b0;       * anyus *
116                         op1_res = regs1;
117                 end*/
118                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
119                         cpsr = incpsr;
120                 end
121                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
122                         cpsr = incpsr;
123                 end
124                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
125                         cpsr = incpsr;
126                 end
127                 32'b????00??????????????????????????: begin /* ALU */
128                         read_1 = insn[3:0];   /* Rm */
129                         read_2 = insn[11:8];  /* Rs for shift */
130                         if(insn[25]) begin     /* the constant case */
131                                 cpsr = incpsr;
132                                 op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
133                         end else begin
134                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
135                                 op1_res = shift_res;
136                         end
137                 end
138                 32'b????00010?00????????00001001????: begin /* Atomic swap */
139                         read_1 = insn[3:0];   /* Rm */
140                         read_2 = 4'b0;        /* anyus */
141                         op1_res = regs1;
142                 end
143                 32'b????000100101111111111110001????: begin /* Branch and exchange */
144                         cpsr = incpsr;
145                 end
146                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
147                         read_1 = insn[3:0];
148                         read_2 = 4'b0;
149                         op1_res = regs1;
150                         cpsr = incpsr;
151                 end
152                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
153                         
154                         read_1 = insn[3:0];
155                         op1_res = {24'b0, insn[11:8], insn[3:0]};
156                         cpsr = incpsr;
157                 end
158                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
159                         /* eat shit */
160                 end
161                 32'b????01??????????????????????????: begin /* Single data transfer */
162                         read_1 = insn[3:0];   /* Rm */
163                         if(insn[25]) begin
164                                 op1_res = {20'b0, insn[11:0]};
165                                 cpsr = incpsr;
166                         end else begin
167                                 op1_res = shift_res;
168                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
169                         end
170                 end
171                 32'b????100?????????????????????????: begin /* Block data transfer */
172                         op1_res = {16'b0, insn[15:0]};
173                         cpsr = incpsr;
174                 end
175                 32'b????101?????????????????????????: begin /* Branch */
176                         op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
177                         cpsr = incpsr;
178                 end
179                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
180                         op1_res = {24'b0, insn[7:0]};
181                         cpsr = incpsr;
182                 end
183                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
184                         cpsr = incpsr;
185                 end
186                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
187                         cpsr = incpsr;
188                 end
189                 32'b????1111????????????????????????: begin /* SWI */
190                         cpsr = incpsr;
191                 end
192                 default: begin end
193                 endcase
194         end
195
196         always @ (posedge clk) begin
197                 op0 <= regs0;   /* Rn - always */
198                 op1 <= op1_res; /* 'operand 2' - Rm */
199                 op2 <= regs2;   /* thirdedge - Rs */
200                 outcpsr <= cpsr;
201         end
202
203 endmodule
204
205 module IHATEARMSHIFT(
206         input [31:0] insn,
207         input [31:0] operand,
208         input [31:0] reg_amt,
209         input cflag_in,
210         output [31:0] res,
211         output cflag_out
212 );
213         wire [5:0] shift_amt;
214         wire elanus;
215
216
217         /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
218         always @(*)
219                 if(insn[4]) begin
220                         shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
221                         elanus = 1'b1;
222                 end else begin
223                         shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
224                         elanus = 1'b0;
225                 end
226         
227         always @(*)
228                 case (insn[6:5]) /* shift type */
229                 `SHIFT_LSL: begin
230                         {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
231                 end
232                 `SHIFT_LSR: begin
233                         {res, cflag_out} = {operand, cflag_in} >> shift_amt;
234                 end
235                 `SHIFT_ASR: begin
236                         {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
237                 end
238                 `SHIFT_ROR: begin
239                         if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
240                                 res = {cflag_in, operand[31:1]};
241                                 cflag_out = operand[0];
242                         end else if(shift_amt == 6'b0) begin
243                                 res = operand;
244                                 cflag_out = cflag_in;
245                         end else begin
246                                 res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
247                                 cflag_out = operand[shift_amt[4:0] - 5'b1];
248                         end
249                 end
250                 endcase
251 endmodule
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