[firearm.git] / Execute.v

module Execute(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input stall,
	input flush,
	
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] cpsr,
	input [31:0] spsr,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input carry,
	
	output reg outstall = 0,
	output reg outbubble = 1,
	output reg [31:0] outcpsr = 0,
	output reg [31:0] outspsr = 0,
	output reg write_reg = 1'bx,
	output reg [3:0] write_num = 4'bxxxx,
	output reg [31:0] write_data = 32'hxxxxxxxx
	);
	
	reg mult_start;
	reg [31:0] mult_acc0, mult_in0, mult_in1;
	wire mult_done;
	wire [31:0] mult_result;
	
	reg [31:0] alu_in0, alu_in1;
	reg [3:0] alu_op;
	reg alu_setflags;
	wire [31:0] alu_result, alu_outcpsr;
	wire alu_setres;
	
	reg next_outbubble;
	reg [31:0] next_outcpsr, next_outspsr;
	reg next_write_reg;
	reg [3:0] next_write_num;
	reg [31:0] next_write_data;
	
	Multiplier multiplier(
		.clk(clk), .Nrst(Nrst),
		.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
		.in1(mult_in1), .done(mult_done), .result(mult_result));
	
	ALU alu(
		.clk(clk), .Nrst(Nrst),
		.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
		.setflags(alu_setflags), .shifter_carry(carry),
		.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
	
	always @(posedge clk)
	begin
		if (!stall)
		begin
			outbubble <= next_outbubble;
			outcpsr <= next_outcpsr;
			outspsr <= next_outspsr;
			write_reg <= next_write_reg;
			write_num <= next_write_num;
			write_data <= next_write_data;
		end
	end

	reg prevstall = 0;
	always @(posedge clk)
		prevstall <= outstall;

	always @(*)
	begin
		outstall = stall;
		next_outbubble = inbubble;
		next_outcpsr = cpsr;
		next_outspsr = spsr;
		next_write_reg = 0;
		next_write_num = 4'hx;
		next_write_data = 32'hxxxxxxxx;
	
		mult_start = 0;
		mult_acc0 = 32'hxxxxxxxx;
		mult_in0 = 32'hxxxxxxxx;
		mult_in1 = 32'hxxxxxxxx;
	
		alu_in0 = 32'hxxxxxxxx;
		alu_in1 = 32'hxxxxxxxx;
		alu_op = 4'hx;	/* hax! */
		alu_setflags = 1'bx;
		
		casez (insn)
		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			if (!prevstall && !inbubble)
			begin
				mult_start = 1;
				mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
				mult_in0 = op1 /* Rm */;
				mult_in1 = op2 /* Rs */;
				$display("New MUL instruction");
			end
			outstall = stall | ((!prevstall | !mult_done) && !inbubble);
			next_outbubble = inbubble | !mult_done | !prevstall;
			next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
			next_write_reg = 1;
			next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
			next_write_data = mult_result;
		end
//		`DECODE_ALU_MUL_LONG,	/* Multiply long */
		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
		begin
			next_write_reg = 1;
			next_write_num = insn[15:12];
			if (insn[22] /* Ps */)
				next_write_data = spsr;
			else
				next_write_data = cpsr;
		end
		`DECODE_ALU_MSR,	/* MSR (Transfer register to PSR) */
		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
			if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))	/* flags only */
			begin
				if (insn[22] /* Ps */)
					next_outspsr = {op0[31:29], spsr[28:0]};
				else
					next_outcpsr = {op0[31:29], cpsr[28:0]};
			end else begin
				if (insn[22] /* Ps */)
					next_outspsr = op0;
				else
					next_outcpsr = op0;
			end
		`DECODE_ALU_SWP,	/* Atomic swap */
		`DECODE_ALU_BX,		/* Branch */
		`DECODE_ALU_HDATA_REG,	/* Halfword transfer - register offset */
		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
		begin end
		`DECODE_ALU:		/* ALU */
		begin
			alu_in0 = op0;
			alu_in1 = op1;
			alu_op = insn[24:21];
			alu_setflags = insn[20] /* S */;
			
			if (alu_setres) begin
				next_write_reg = 1;
				next_write_num = insn[15:12] /* Rd */;
				next_write_data = alu_result;
			end
			
			next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
		end
		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
		`DECODE_LDRSTR,		/* Single data transfer */
		`DECODE_LDMSTM,		/* Block data transfer */
		`DECODE_BRANCH,		/* Branch */
		`DECODE_LDCSTC,		/* Coprocessor data transfer */
		`DECODE_CDP,		/* Coprocessor data op */
		`DECODE_MRCMCR,		/* Coprocessor register transfer */
		`DECODE_SWI:		/* SWI */
		begin end
		default:		/* X everything else out */
		begin end
		endcase
	end
endmodule

module Multiplier(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input start,
	input [31:0] acc0,
	input [31:0] in0,
	input [31:0] in1,
	
	output reg done = 0,
	output reg [31:0] result);
	
	reg [31:0] bitfield;
	reg [31:0] multiplicand;
	reg [31:0] acc;
	
	always @(posedge clk)
	begin
		if (start) begin
			bitfield <= in0;
			multiplicand <= in1;
			acc <= acc0;
			done <= 0;
		end else begin
			bitfield <= {2'b00, bitfield[31:2]};
			multiplicand <= {multiplicand[29:0], 2'b00};
			acc <= acc +
				(bitfield[0] ? multiplicand : 0) +
				(bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
			if (bitfield == 0) begin
				result <= acc;
				done <= 1;
			end
		end
	end
endmodule

module ALU(
	input clk,
	input Nrst,	/* XXX not used yet */

	input [31:0] in0,
	input [31:0] in1,
	input [31:0] cpsr,
	input [3:0] op,
	input setflags,
	input shifter_carry,

	output reg [31:0] result,
	output reg [31:0] cpsr_out,
	output reg setres
);
	wire [31:0] res;
	wire flag_n, flag_z, flag_c, flag_v, setres;
	wire [32:0] sum, diff, rdiff;
	wire sum_v, diff_v, rdiff_v;

	assign sum = {1'b0, in0} + {1'b0, in1};
	assign diff = {1'b0, in0} - {1'b0, in1};
	assign rdiff = {1'b0, in1} + {1'b0, in0};
	assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
	assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
	assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);

	always @(*) begin
		res = 32'hxxxxxxxx;
		setres = 1'bx;
		flag_c = cpsr[`CPSR_C];
		flag_v = cpsr[`CPSR_V];
		case(op)
		`ALU_AND: begin
			result = in0 & in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_EOR: begin
			result = in0 ^ in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_SUB: begin
			{flag_c, result} = diff;
			flag_v = diff_v;
			setres = 1'b1;
		end
		`ALU_RSB: begin
			{flag_c, result} = rdiff;
			flag_v = rdiff_v;
			setres = 1'b1;
		end
		`ALU_ADD: begin
			{flag_c, result} = sum;
			flag_v = sum_v;
			setres = 1'b1;
		end
		`ALU_ADC: begin
			{flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
			flag_v = sum_v | (~sum[31] & result[31]);
			setres = 1'b1;
		end
		`ALU_SBC: begin
			{flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
			flag_v = diff_v | (diff[31] & ~result[31]);
			setres = 1'b1;
		end
		`ALU_RSC: begin
			{flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
			flag_v = rdiff_v | (rdiff[31] & ~result[31]);
			setres = 1'b1;
		end
		`ALU_TST: begin
			result = in0 & in1;
			flag_c = shifter_carry;
			setres = 1'b0;
		end
		`ALU_TEQ: begin
			result = in0 ^ in1;
			flag_c = shifter_carry;
			setres = 1'b0;
		end
		`ALU_CMP: begin
			{flag_c, result} = diff;
			flag_v = diff_v;
			setres = 1'b0;
		end
		`ALU_CMN: begin
			{flag_c, result} = sum;
			flag_v = sum_v;
			setres = 1'b0;
		end
		`ALU_ORR: begin
			result = in0 | in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_MOV: begin
			result = in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_BIC: begin
			result = in0 & (~in1);
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_MVN: begin
			result = ~in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		endcase
		
		flag_z = (result == 0);
		flag_n = result[31];
		
		cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
	end
endmodule
Commit	Line	Data
5b3daee2 JW	1	module Execute(
	2	input clk,
	3	input Nrst, /* XXX not used yet */
	4
	5	input stall,
	6	input flush,
	7
	8	input inbubble,
	9	input [31:0] pc,
	10	input [31:0] insn,
	11	input [31:0] cpsr,
cb0428b6	12	input [31:0] spsr,
3f5cefe1 JW	13	input [31:0] op0,
	14	input [31:0] op1,
	15	input [31:0] op2,
	16	input carry,
5b3daee2 JW	17
5b3daee2 JW	18	output reg outstall = 0,
bc572c5f	19	output reg outbubble = 1,
6e3dfd79	20	output reg [31:0] outcpsr = 0,
cb0428b6	21	output reg [31:0] outspsr = 0,
bc572c5f JW	22	output reg write_reg = 1'bx,
	23	output reg [3:0] write_num = 4'bxxxx,
	24	output reg [31:0] write_data = 32'hxxxxxxxx
5b3daee2	25	);
5b3daee2	26
bc572c5f JW	27	reg mult_start;
	28	reg [31:0] mult_acc0, mult_in0, mult_in1;
	29	wire mult_done;
	30	wire [31:0] mult_result;
	31
2b091cd4 JW	32	reg [31:0] alu_in0, alu_in1;
	33	reg [3:0] alu_op;
	34	reg alu_setflags;
6e3dfd79	35	wire [31:0] alu_result, alu_outcpsr;
732b7730 JW	36	wire alu_setres;
	37
	38	reg next_outbubble;
cb0428b6	39	reg [31:0] next_outcpsr, next_outspsr;
732b7730 JW	40	reg next_write_reg;
	41	reg [3:0] next_write_num;
	42	reg [31:0] next_write_data;
6e3dfd79	43
bc572c5f JW	44	Multiplier multiplier(
	45	.clk(clk), .Nrst(Nrst),
	46	.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
	47	.in1(mult_in1), .done(mult_done), .result(mult_result));
6e3dfd79 JW	48
	49	ALU alu(
	50	.clk(clk), .Nrst(Nrst),
	51	.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
	52	.setflags(alu_setflags), .shifter_carry(carry),
732b7730 JW	53	.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
	54
	55	always @(posedge clk)
	56	begin
	57	if (!stall)
	58	begin
	59	outbubble <= next_outbubble;
	60	outcpsr <= next_outcpsr;
cb0428b6	61	outspsr <= next_outspsr;
732b7730 JW	62	write_reg <= next_write_reg;
	63	write_num <= next_write_num;
	64	write_data <= next_write_data;
	65	end
	66	end
2b091cd4	67
af096d96 JW	68	reg prevstall = 0;
	69	always @(posedge clk)
	70	prevstall <= outstall;
	71
2b091cd4	72	always @(*)
732b7730 JW	73	begin
	74	outstall = stall;
	75	next_outbubble = inbubble;
	76	next_outcpsr = cpsr;
cb0428b6	77	next_outspsr = spsr;
732b7730 JW	78	next_write_reg = 0;
	79	next_write_num = 4'hx;
	80	next_write_data = 32'hxxxxxxxx;
	81
af096d96 JW	82	mult_start = 0;
	83	mult_acc0 = 32'hxxxxxxxx;
	84	mult_in0 = 32'hxxxxxxxx;
	85	mult_in1 = 32'hxxxxxxxx;
	86
732b7730 JW	87	alu_in0 = 32'hxxxxxxxx;
	88	alu_in1 = 32'hxxxxxxxx;
	89	alu_op = 4'hx; /* hax! */
	90	alu_setflags = 1'bx;
	91
2b091cd4	92	casez (insn)
af096d96 JW	93	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	94	begin
	95	if (!prevstall && !inbubble)
	96	begin
	97	mult_start = 1;
	98	mult_acc0 = insn[21] /* A / ? op0 / Rn */ : 32'h0;
	99	mult_in0 = op1 /* Rm */;
	100	mult_in1 = op2 /* Rs */;
	101	$display("New MUL instruction");
	102	end
	103	outstall = stall \| ((!prevstall \| !mult_done) && !inbubble);
	104	next_outbubble = inbubble \| !mult_done \| !prevstall;
	105	next_outcpsr = insn[20] /* S / ? {mult_result[31] / N /, mult_result == 0 / Z /, 1'b0 / C /, cpsr[28] / V */, cpsr[27:0]} : cpsr;
	106	next_write_reg = 1;
	107	next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
	108	next_write_data = mult_result;
	109	end
2b091cd4	110	// `DECODE_ALU_MUL_LONG, /* Multiply long */
cb0428b6 JW	111	`DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
	112	begin
	113	next_write_reg = 1;
	114	next_write_num = insn[15:12];
	115	if (insn[22] /* Ps */)
	116	next_write_data = spsr;
	117	else
	118	next_write_data = cpsr;
	119	end
2b091cd4	120	`DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
cb0428b6 JW	121	`DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
	122	if ((cpsr[4:0] == `MODE_USR) \|\| (insn[16] /* that random bit / == 1'b0)) / flags only */
	123	begin
	124	if (insn[22] /* Ps */)
	125	next_outspsr = {op0[31:29], spsr[28:0]};
	126	else
	127	next_outcpsr = {op0[31:29], cpsr[28:0]};
	128	end else begin
	129	if (insn[22] /* Ps */)
	130	next_outspsr = op0;
	131	else
	132	next_outcpsr = op0;
	133	end
2b091cd4 JW	134	`DECODE_ALU_SWP, /* Atomic swap */
	135	`DECODE_ALU_BX, /* Branch */
	136	`DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
732b7730 JW	137	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
	138	begin end
	139	`DECODE_ALU: /* ALU */
	140	begin
	141	alu_in0 = op0;
	142	alu_in1 = op1;
	143	alu_op = insn[24:21];
cb0428b6	144	alu_setflags = insn[20] /* S */;
732b7730 JW	145
	146	if (alu_setres) begin
	147	next_write_reg = 1;
	148	next_write_num = insn[15:12] /* Rd */;
	149	next_write_data = alu_result;
	150	end
	151
cb0428b6	152	next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
732b7730	153	end
2b091cd4 JW	154	`DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
	155	`DECODE_LDRSTR, /* Single data transfer */
	156	`DECODE_LDMSTM, /* Block data transfer */
	157	`DECODE_BRANCH, /* Branch */
	158	`DECODE_LDCSTC, /* Coprocessor data transfer */
	159	`DECODE_CDP, /* Coprocessor data op */
	160	`DECODE_MRCMCR, /* Coprocessor register transfer */
	161	`DECODE_SWI: /* SWI */
	162	begin end
	163	default: /* X everything else out */
	164	begin end
	165	endcase
732b7730	166	end
5b3daee2	167	endmodule
07fbfa80 JW	168
	169	module Multiplier(
	170	input clk,
	171	input Nrst, /* XXX not used yet */
	172
	173	input start,
	174	input [31:0] acc0,
	175	input [31:0] in0,
	176	input [31:0] in1,
	177
	178	output reg done = 0,
	179	output reg [31:0] result);
	180
	181	reg [31:0] bitfield;
	182	reg [31:0] multiplicand;
	183	reg [31:0] acc;
	184
	185	always @(posedge clk)
	186	begin
	187	if (start) begin
	188	bitfield <= in0;
	189	multiplicand <= in1;
	190	acc <= acc0;
	191	done <= 0;
	192	end else begin
	193	bitfield <= {2'b00, bitfield[31:2]};
	194	multiplicand <= {multiplicand[29:0], 2'b00};
	195	acc <= acc +
	196	(bitfield[0] ? multiplicand : 0) +
	197	(bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
	198	if (bitfield == 0) begin
	199	result <= acc;
	200	done <= 1;
	201	end
	202	end
	203	end
	204	endmodule
879a3986	205
879a3986 CL	206	module ALU(
	207	input clk,
	208	input Nrst, /* XXX not used yet */
	209
	210	input [31:0] in0,
	211	input [31:0] in1,
	212	input [31:0] cpsr,
	213	input [3:0] op,
	214	input setflags,
	215	input shifter_carry,
	216
	217	output reg [31:0] result,
	218	output reg [31:0] cpsr_out,
732b7730	219	output reg setres
879a3986 CL	220	);
	221	wire [31:0] res;
	222	wire flag_n, flag_z, flag_c, flag_v, setres;
	223	wire [32:0] sum, diff, rdiff;
793482e9	224	wire sum_v, diff_v, rdiff_v;
879a3986 CL	225
	226	assign sum = {1'b0, in0} + {1'b0, in1};
	227	assign diff = {1'b0, in0} - {1'b0, in1};
	228	assign rdiff = {1'b0, in1} + {1'b0, in0};
793482e9 CL	229	assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
	230	assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
	231	assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
879a3986	232
879a3986 CL	233	always @(*) begin
	234	res = 32'hxxxxxxxx;
	235	setres = 1'bx;
	236	flag_c = cpsr[`CPSR_C];
	237	flag_v = cpsr[`CPSR_V];
	238	case(op)
	239	`ALU_AND: begin
732b7730	240	result = in0 & in1;
879a3986 CL	241	flag_c = shifter_carry;
	242	setres = 1'b1;
	243	end
	244	`ALU_EOR: begin
732b7730	245	result = in0 ^ in1;
879a3986 CL	246	flag_c = shifter_carry;
	247	setres = 1'b1;
	248	end
	249	`ALU_SUB: begin
732b7730	250	{flag_c, result} = diff;
793482e9	251	flag_v = diff_v;
879a3986 CL	252	setres = 1'b1;
	253	end
	254	`ALU_RSB: begin
732b7730	255	{flag_c, result} = rdiff;
793482e9	256	flag_v = rdiff_v;
879a3986 CL	257	setres = 1'b1;
	258	end
	259	`ALU_ADD: begin
732b7730	260	{flag_c, result} = sum;
793482e9	261	flag_v = sum_v;
879a3986 CL	262	setres = 1'b1;
	263	end
	264	`ALU_ADC: begin
732b7730	265	{flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
793482e9	266	flag_v = sum_v \| (~sum[31] & result[31]);
879a3986 CL	267	setres = 1'b1;
	268	end
	269	`ALU_SBC: begin
732b7730	270	{flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
793482e9	271	flag_v = diff_v \| (diff[31] & ~result[31]);
879a3986 CL	272	setres = 1'b1;
	273	end
	274	`ALU_RSC: begin
732b7730	275	{flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
793482e9	276	flag_v = rdiff_v \| (rdiff[31] & ~result[31]);
879a3986 CL	277	setres = 1'b1;
	278	end
	279	`ALU_TST: begin
732b7730	280	result = in0 & in1;
879a3986 CL	281	flag_c = shifter_carry;
	282	setres = 1'b0;
	283	end
	284	`ALU_TEQ: begin
732b7730	285	result = in0 ^ in1;
879a3986 CL	286	flag_c = shifter_carry;
	287	setres = 1'b0;
	288	end
	289	`ALU_CMP: begin
732b7730	290	{flag_c, result} = diff;
793482e9	291	flag_v = diff_v;
879a3986 CL	292	setres = 1'b0;
	293	end
	294	`ALU_CMN: begin
732b7730	295	{flag_c, result} = sum;
793482e9	296	flag_v = sum_v;
879a3986 CL	297	setres = 1'b0;
	298	end
	299	`ALU_ORR: begin
732b7730	300	result = in0 \| in1;
879a3986 CL	301	flag_c = shifter_carry;
	302	setres = 1'b1;
	303	end
	304	`ALU_MOV: begin
732b7730	305	result = in1;
879a3986 CL	306	flag_c = shifter_carry;
	307	setres = 1'b1;
	308	end
	309	`ALU_BIC: begin
732b7730	310	result = in0 & (~in1);
879a3986 CL	311	flag_c = shifter_carry;
	312	setres = 1'b1;
	313	end
	314	`ALU_MVN: begin
732b7730	315	result = ~in1;
879a3986 CL	316	flag_c = shifter_carry;
	317	setres = 1'b1;
	318	end
	319	endcase
732b7730 JW	320
	321	flag_z = (result == 0);
	322	flag_n = result[31];
	323
	324	cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986	325	end
879a3986	326	endmodule