Memory: Change offset latch in LDM so that there is no flutter if DCache cannot get...
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         input flush,
8
9         /* bus interface */
10         output reg [31:0] busaddr,
11         output reg rd_req,
12         output reg wr_req,
13         input rw_wait,
14         output reg [31:0] wr_data,
15         input [31:0] rd_data,
16         output reg [2:0] data_size,
17
18         /* regfile interface */
19         output reg [3:0] st_read,
20         input [31:0] st_data,
21         
22         /* Coprocessor interface */
23         output reg cp_req,
24         input cp_ack,
25         input cp_busy,
26         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
27         input [31:0] cp_read,
28         output reg [31:0] cp_write,
29         
30         /* stage inputs */
31         input inbubble,
32         input [31:0] pc,
33         input [31:0] insn,
34         input [31:0] op0,
35         input [31:0] op1,
36         input [31:0] op2,
37         input [31:0] spsr,
38         input [31:0] cpsr,
39         input write_reg,
40         input [3:0] write_num,
41         input [31:0] write_data,
42
43         /* outputs */
44         output reg outstall,
45         output reg outbubble,
46         output reg [31:0] outpc,
47         output reg [31:0] outinsn,
48         output reg out_write_reg = 1'b0,
49         output reg [3:0] out_write_num = 4'bxxxx,
50         output reg [31:0] out_write_data = 32'hxxxxxxxx,
51         output reg [31:0] outspsr = 32'hxxxxxxxx,
52         output reg [31:0] outcpsr = 32'hxxxxxxxx
53         );
54
55         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
56         reg [31:0] prevaddr;
57         reg [3:0] next_regsel, cur_reg, prev_reg;
58         reg next_writeback;
59
60         reg next_outbubble;     
61         reg next_write_reg;
62         reg [3:0] next_write_num;
63         reg [31:0] next_write_data;
64
65         reg [1:0] lsr_state = 2'b01, next_lsr_state;
66         reg [31:0] align_s1, align_s2, align_rddata;
67
68         reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
69         reg [31:0] lsrh_rddata;
70         reg [15:0] lsrh_rddata_s1;
71         reg [7:0] lsrh_rddata_s2;
72
73         reg [15:0] regs, next_regs;
74         reg [2:0] lsm_state = 3'b001, next_lsm_state;
75         reg [5:0] offset, prev_offset, offset_sel;
76
77         reg [31:0] swp_oldval, next_swp_oldval;
78         reg [1:0] swp_state = 2'b01, next_swp_state;
79
80         always @(posedge clk)
81         begin
82                 outpc <= pc;
83                 outinsn <= insn;
84                 outbubble <= next_outbubble;
85                 out_write_reg <= next_write_reg;
86                 out_write_num <= next_write_num;
87                 out_write_data <= next_write_data;
88                 regs <= next_regs;
89                 prev_reg <= cur_reg;
90                 if (!rw_wait)
91                         prev_offset <= offset;
92                 prev_raddr <= raddr;
93                 outcpsr <= next_outcpsr;
94                 outspsr <= spsr;
95                 swp_state <= next_swp_state;
96                 lsm_state <= next_lsm_state;
97                 lsr_state <= next_lsr_state;
98                 lsrh_state <= next_lsrh_state;
99                 prevaddr <= addr;
100         end
101         
102         reg delayedflush = 0;
103         always @(posedge clk)
104                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
105                         delayedflush <= 1;
106                 else if (!outstall /* anything has been handled this time around */)
107                         delayedflush <= 0;
108
109         always @(*)
110         begin
111                 addr = prevaddr;
112                 raddr = 32'hxxxxxxxx;
113                 rd_req = 1'b0;
114                 wr_req = 1'b0;
115                 wr_data = 32'hxxxxxxxx;
116                 busaddr = 32'hxxxxxxxx;
117                 data_size = 3'bxxx;
118                 outstall = 1'b0;
119                 next_write_reg = write_reg;
120                 next_write_num = write_num;
121                 next_write_data = write_data;
122                 next_outbubble = inbubble;
123                 next_regs = regs;
124                 cp_req = 1'b0;
125                 cp_rnw = 1'bx;
126                 cp_write = 32'hxxxxxxxx;
127                 offset = prev_offset;
128                 next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
129                 lsrh_rddata = 32'hxxxxxxxx;
130                 lsrh_rddata_s1 = 16'hxxxx;
131                 lsrh_rddata_s2 = 8'hxx;
132                 next_lsm_state = lsm_state;
133                 next_lsr_state = lsr_state;
134                 next_lsrh_state = lsrh_state;
135                 next_swp_oldval = swp_oldval;
136                 next_swp_state = swp_state;
137                 cur_reg = prev_reg;
138
139                 /* XXX shit not given about endianness */
140                 casez(insn)
141                 `DECODE_ALU_SWP: if(!inbubble) begin
142                         outstall = rw_wait;
143                         next_outbubble = rw_wait;
144                         busaddr = {op0[31:2], 2'b0};
145                         data_size = insn[22] ? 3'b001 : 3'b100;
146                         case(swp_state)
147                         2'b01: begin
148                                 rd_req = 1'b1;
149                                 outstall = 1'b1;
150                                 if(!rw_wait) begin
151                                         next_swp_state = 2'b10;
152                                         next_swp_oldval = rd_data;
153                                 end
154                         end
155                         2'b10: begin
156                                 wr_req = 1'b1;
157                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
158                                 next_write_reg = 1'b1;
159                                 next_write_num = insn[15:12];
160                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
161                                 if(!rw_wait)
162                                         next_swp_state = 2'b01;
163                         end
164                         default: begin end
165                         endcase
166                 end
167                 `DECODE_ALU_HDATA_REG,
168                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
169                         next_outbubble = rw_wait;
170                         outstall = rw_wait;
171                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
172                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
173                         busaddr = raddr;
174                         /* rotate to correct position */
175                         case(insn[6:5])
176                         2'b00: begin end /* swp */
177                         2'b01: begin /* unsigned half */
178                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
179                                 data_size = 3'b010;
180                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
181                         end
182                         2'b10: begin /* signed byte */
183                                 wr_data = {4{op2[7:0]}};
184                                 data_size = 3'b001;
185                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
186                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
187                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
188                         end
189                         2'b11: begin /* signed half */
190                                 wr_data = {2{op2[15:0]}};
191                                 data_size = 3'b010;
192                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
193                         end
194                         endcase
195
196                         case(lsrh_state)
197                         2'b01: begin
198                                 rd_req = insn[20];
199                                 wr_req = ~insn[20];
200                                 next_write_num = insn[15:12];
201                                 next_write_data = lsrh_rddata;
202                                 if(insn[20]) begin
203                                         next_write_reg = 1'b1;
204                                 end
205                                 if(insn[21] | !insn[24]) begin
206                                         outstall = 1'b1;
207                                         if(!rw_wait)
208                                                 next_lsrh_state = 2'b10;
209                                 end
210                         end
211                         2'b10: begin
212                                 next_write_reg = 1'b1;
213                                 next_write_num = insn[19:16];
214                                 next_write_data = addr;
215                                 next_lsrh_state = 2'b10;
216                         end
217                         default: begin end
218                         endcase
219                 end
220                 `DECODE_LDRSTR_UNDEFINED: begin end
221                 `DECODE_LDRSTR: if(!inbubble) begin
222                         next_outbubble = rw_wait;
223                         outstall = rw_wait;
224                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
225                         raddr = insn[24] ? addr : op0; /* pre/post increment */
226                         busaddr = raddr;
227                         /* rotate to correct position */
228                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
229                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
230                         /* select byte or word */
231                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
232                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
233                         data_size = insn[22] ? 3'b001 : 3'b100;
234                         case(lsr_state)
235                         2'b01: begin
236                                 rd_req = insn[20];
237                                 wr_req = ~insn[20];
238                                 next_write_reg = 1'b1;
239                                 next_write_num = insn[15:12];
240                                 if(insn[20]) begin
241                                         next_write_data = align_rddata;
242                                 end
243                                 if(insn[21] | !insn[24]) begin
244                                         outstall = 1'b1;
245                                         if(!rw_wait)
246                                                 next_lsr_state = 2'b10;
247                                 end
248                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
249                         end
250                         2'b10: begin
251                                 next_write_reg = 1'b1;
252                                 next_write_num = insn[19:16];
253                                 next_write_data = addr;
254                                 next_lsr_state = 2'b01;
255                         end
256                         default: begin end
257                         endcase
258                 end
259                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
260                 `DECODE_LDMSTM: if(!inbubble) begin
261                         outstall = rw_wait;
262                         next_outbubble = rw_wait;
263                         data_size = 3'b100;
264                         case(lsm_state)
265                         3'b001: begin
266 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
267                                 /** verilator can suck my dick */
268                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
269                                 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
270                                                                             op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
271                                 offset = 6'b0;
272                                 outstall = 1'b1;
273                                 next_lsm_state = 3'b010;
274                         end
275                         3'b010: begin
276                                 rd_req = insn[20];
277                                 wr_req = ~insn[20];
278                                 casez(regs)
279                                 16'b???????????????1: begin
280                                         cur_reg = 4'h0;
281                                         next_regs = {regs[15:1], 1'b0};
282                                 end
283                                 16'b??????????????10: begin
284                                         cur_reg = 4'h1;
285                                         next_regs = {regs[15:2], 2'b0};
286                                 end
287                                 16'b?????????????100: begin
288                                         cur_reg = 4'h2;
289                                         next_regs = {regs[15:3], 3'b0};
290                                 end
291                                 16'b????????????1000: begin
292                                         cur_reg = 4'h3;
293                                         next_regs = {regs[15:4], 4'b0};
294                                 end
295                                 16'b???????????10000: begin
296                                         cur_reg = 4'h4;
297                                         next_regs = {regs[15:5], 5'b0};
298                                 end
299                                 16'b??????????100000: begin
300                                         cur_reg = 4'h5;
301                                         next_regs = {regs[15:6], 6'b0};
302                                 end
303                                 16'b?????????1000000: begin
304                                         cur_reg = 4'h6;
305                                         next_regs = {regs[15:7], 7'b0};
306                                 end
307                                 16'b????????10000000: begin
308                                         cur_reg = 4'h7;
309                                         next_regs = {regs[15:8], 8'b0};
310                                 end
311                                 16'b???????100000000: begin
312                                         cur_reg = 4'h8;
313                                         next_regs = {regs[15:9], 9'b0};
314                                 end
315                                 16'b??????1000000000: begin
316                                         cur_reg = 4'h9;
317                                         next_regs = {regs[15:10], 10'b0};
318                                 end
319                                 16'b?????10000000000: begin
320                                         cur_reg = 4'hA;
321                                         next_regs = {regs[15:11], 11'b0};
322                                 end
323                                 16'b????100000000000: begin
324                                         cur_reg = 4'hB;
325                                         next_regs = {regs[15:12], 12'b0};
326                                 end
327                                 16'b???1000000000000: begin
328                                         cur_reg = 4'hC;
329                                         next_regs = {regs[15:13], 13'b0};
330                                 end
331                                 16'b??10000000000000: begin
332                                         cur_reg = 4'hD;
333                                         next_regs = {regs[15:14], 14'b0};
334                                 end
335                                 16'b?100000000000000: begin
336                                         cur_reg = 4'hE;
337                                         next_regs = {regs[15], 15'b0};
338                                 end
339                                 16'b1000000000000000: begin
340                                         cur_reg = 4'hF;
341                                         next_regs = 16'b0;
342                                 end
343                                 default: begin
344                                         cur_reg = 4'hx;
345                                         next_regs = 16'b0;
346                                 end
347                                 endcase
348                                 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
349                                 if(cur_reg == 4'hF && insn[22]) begin
350                                         next_outcpsr = spsr;
351                                 end
352
353                                 offset = prev_offset + 6'h4;
354                                 offset_sel = insn[24] ? offset : prev_offset;
355                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
356                                 if(insn[20]) begin
357                                         next_write_reg = !rw_wait;
358                                         next_write_num = cur_reg;
359                                         next_write_data = rd_data;
360                                 end
361                                 if (rw_wait) begin
362                                         next_regs = regs;
363                                         cur_reg = prev_reg;     /* whoops, do this one again */
364                                 end
365
366                                 st_read = cur_reg;
367                                 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
368                                 busaddr = raddr;
369                                 
370                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
371
372                                 outstall = 1'b1;
373
374                                 if(next_regs == 16'b0) begin
375                                         next_lsm_state = 3'b100;
376                                 end
377                         end
378                         3'b100: begin
379                                 next_write_reg = insn[21] /* writeback */;
380                                 next_write_num = insn[19:16];
381                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
382                                 next_lsm_state = 3'b001;
383                                 $display("LDMSTM: Stage 3: Writing back");
384                         end
385                         default: $stop;
386                         endcase
387                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
388                 end
389                 `DECODE_LDCSTC: if(!inbubble) begin
390                         $display("WARNING: Unimplemented LDCSTC");
391                 end
392                 `DECODE_CDP: if(!inbubble) begin
393                         cp_req = 1;
394                         if (cp_busy) begin
395                                 outstall = 1;
396                                 next_outbubble = 1;
397                         end
398                         if (!cp_ack) begin
399                                 /* XXX undefined instruction trap */
400                                 $display("WARNING: Possible CDP undefined instruction");
401                         end
402                 end
403                 `DECODE_MRCMCR: if(!inbubble) begin
404                         cp_req = 1;
405                         cp_rnw = insn[20] /* L */;
406                         if (insn[20] == 0 /* store to coprocessor */)
407                                 cp_write = op0;
408                         else begin
409                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
410                                         next_write_reg = 1'b1;
411                                         next_write_num = insn[15:12];
412                                         next_write_data = cp_read;
413                                 end else
414                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
415                         end
416                         if (cp_busy) begin
417                                 outstall = 1;
418                                 next_outbubble = 1;
419                         end
420                         if (!cp_ack) begin
421                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
422                         end
423                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
424                 end
425                 default: begin end
426                 endcase
427                 
428                 if ((flush || delayedflush) && !outstall)
429                         next_outbubble = 1'b1;
430         end
431 endmodule
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