Memory: Change offset latch in LDM so that there is no flutter if DCache cannot get...
[firearm.git] / Memory.v
CommitLineData
b3bb2fb8
CL
1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
b3bb2fb8 6
ab7ee9fc
JW
7 input flush,
8
b3bb2fb8
CL
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
9fc6c23c 16 output reg [2:0] data_size,
b3bb2fb8
CL
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
a02ca509 21
979f2bd7
JW
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
804dc0bc 26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
43e4332c
JW
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
979f2bd7 29
a02ca509
JW
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
e68b2378
JW
34 input [31:0] op0,
35 input [31:0] op1,
6d0f9d82 36 input [31:0] op2,
efd1aa13
CL
37 input [31:0] spsr,
38 input [31:0] cpsr,
a02ca509
JW
39 input write_reg,
40 input [3:0] write_num,
41 input [31:0] write_data,
b3bb2fb8 42
a02ca509
JW
43 /* outputs */
44 output reg outstall,
45 output reg outbubble,
b3bb2fb8 46 output reg [31:0] outpc,
a02ca509
JW
47 output reg [31:0] outinsn,
48 output reg out_write_reg = 1'b0,
49 output reg [3:0] out_write_num = 4'bxxxx,
efd1aa13 50 output reg [31:0] out_write_data = 32'hxxxxxxxx,
ab7ee9fc
JW
51 output reg [31:0] outspsr = 32'hxxxxxxxx,
52 output reg [31:0] outcpsr = 32'hxxxxxxxx
a02ca509 53 );
b3bb2fb8 54
efd1aa13 55 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
666ceb03 56 reg [31:0] prevaddr;
e08b748a 57 reg [3:0] next_regsel, cur_reg, prev_reg;
9a0d0e43 58 reg next_writeback;
e08b748a 59
804dc0bc
JW
60 reg next_outbubble;
61 reg next_write_reg;
62 reg [3:0] next_write_num;
63 reg [31:0] next_write_data;
74d3729c 64
9a0d0e43 65 reg [1:0] lsr_state = 2'b01, next_lsr_state;
666ceb03
CL
66 reg [31:0] align_s1, align_s2, align_rddata;
67
68 reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
69 reg [31:0] lsrh_rddata;
70 reg [15:0] lsrh_rddata_s1;
71 reg [7:0] lsrh_rddata_s2;
9a0d0e43 72
b783a475 73 reg [15:0] regs, next_regs;
9a0d0e43 74 reg [2:0] lsm_state = 3'b001, next_lsm_state;
b114e03f 75 reg [5:0] offset, prev_offset, offset_sel;
74d3729c 76
9a0d0e43
CL
77 reg [31:0] swp_oldval, next_swp_oldval;
78 reg [1:0] swp_state = 2'b01, next_swp_state;
a02ca509
JW
79
80 always @(posedge clk)
81 begin
82 outpc <= pc;
83 outinsn <= insn;
c65110a8
JW
84 outbubble <= next_outbubble;
85 out_write_reg <= next_write_reg;
86 out_write_num <= next_write_num;
87 out_write_data <= next_write_data;
e68b2378 88 regs <= next_regs;
e08b748a 89 prev_reg <= cur_reg;
95704fd3
JW
90 if (!rw_wait)
91 prev_offset <= offset;
b114e03f 92 prev_raddr <= raddr;
ab7ee9fc
JW
93 outcpsr <= next_outcpsr;
94 outspsr <= spsr;
9a0d0e43 95 swp_state <= next_swp_state;
666ceb03
CL
96 lsm_state <= next_lsm_state;
97 lsr_state <= next_lsr_state;
98 lsrh_state <= next_lsrh_state;
99 prevaddr <= addr;
a02ca509 100 end
d73619a2
JW
101
102 reg delayedflush = 0;
103 always @(posedge clk)
104 if (flush && outstall /* halp! I can't do it now, maybe later? */)
105 delayedflush <= 1;
106 else if (!outstall /* anything has been handled this time around */)
107 delayedflush <= 0;
b3bb2fb8
CL
108
109 always @(*)
110 begin
666ceb03 111 addr = prevaddr;
b3bb2fb8
CL
112 raddr = 32'hxxxxxxxx;
113 rd_req = 1'b0;
114 wr_req = 1'b0;
115 wr_data = 32'hxxxxxxxx;
116 busaddr = 32'hxxxxxxxx;
2bcc55d5 117 data_size = 3'bxxx;
b3bb2fb8 118 outstall = 1'b0;
a02ca509
JW
119 next_write_reg = write_reg;
120 next_write_num = write_num;
121 next_write_data = write_data;
c65110a8 122 next_outbubble = inbubble;
9a0d0e43 123 next_regs = regs;
979f2bd7 124 cp_req = 1'b0;
43e4332c
JW
125 cp_rnw = 1'bx;
126 cp_write = 32'hxxxxxxxx;
b114e03f 127 offset = prev_offset;
ab7ee9fc 128 next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
666ceb03 129 lsrh_rddata = 32'hxxxxxxxx;
9fc6c23c
CL
130 lsrh_rddata_s1 = 16'hxxxx;
131 lsrh_rddata_s2 = 8'hxx;
9a0d0e43
CL
132 next_lsm_state = lsm_state;
133 next_lsr_state = lsr_state;
666ceb03 134 next_lsrh_state = lsrh_state;
9a0d0e43
CL
135 next_swp_oldval = swp_oldval;
136 next_swp_state = swp_state;
137 cur_reg = prev_reg;
9f082c0b 138
5989b2f5 139 /* XXX shit not given about endianness */
d73619a2 140 casez(insn)
5989b2f5
CL
141 `DECODE_ALU_SWP: if(!inbubble) begin
142 outstall = rw_wait;
143 next_outbubble = rw_wait;
144 busaddr = {op0[31:2], 2'b0};
2bcc55d5 145 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5
CL
146 case(swp_state)
147 2'b01: begin
148 rd_req = 1'b1;
149 outstall = 1'b1;
150 if(!rw_wait) begin
151 next_swp_state = 2'b10;
152 next_swp_oldval = rd_data;
9a0d0e43 153 end
9a0d0e43 154 end
5989b2f5
CL
155 2'b10: begin
156 wr_req = 1'b1;
2bcc55d5 157 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
5989b2f5
CL
158 next_write_reg = 1'b1;
159 next_write_num = insn[15:12];
2bcc55d5 160 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
5989b2f5
CL
161 if(!rw_wait)
162 next_swp_state = 2'b01;
163 end
164 default: begin end
165 endcase
9a0d0e43 166 end
666ceb03
CL
167 `DECODE_ALU_HDATA_REG,
168 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
169 next_outbubble = rw_wait;
170 outstall = rw_wait;
171 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
172 raddr = insn[24] ? op0 : addr; /* pre/post increment */
173 busaddr = raddr;
174 /* rotate to correct position */
175 case(insn[6:5])
176 2'b00: begin end /* swp */
177 2'b01: begin /* unsigned half */
178 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
2bcc55d5 179 data_size = 3'b010;
666ceb03
CL
180 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
181 end
182 2'b10: begin /* signed byte */
183 wr_data = {4{op2[7:0]}};
2bcc55d5 184 data_size = 3'b001;
666ceb03
CL
185 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
186 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
187 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
188 end
189 2'b11: begin /* signed half */
190 wr_data = {2{op2[15:0]}};
2bcc55d5 191 data_size = 3'b010;
666ceb03
CL
192 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
193 end
194 endcase
195
196 case(lsrh_state)
197 2'b01: begin
198 rd_req = insn[20];
199 wr_req = ~insn[20];
200 next_write_num = insn[15:12];
201 next_write_data = lsrh_rddata;
202 if(insn[20]) begin
203 next_write_reg = 1'b1;
204 end
205 if(insn[21] | !insn[24]) begin
206 outstall = 1'b1;
207 if(!rw_wait)
208 next_lsrh_state = 2'b10;
209 end
210 end
211 2'b10: begin
212 next_write_reg = 1'b1;
213 next_write_num = insn[19:16];
214 next_write_data = addr;
215 next_lsrh_state = 2'b10;
216 end
217 default: begin end
218 endcase
219 end
b3bb2fb8 220 `DECODE_LDRSTR_UNDEFINED: begin end
5989b2f5
CL
221 `DECODE_LDRSTR: if(!inbubble) begin
222 next_outbubble = rw_wait;
223 outstall = rw_wait;
224 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
feb2b5be 225 raddr = insn[24] ? addr : op0; /* pre/post increment */
666ceb03
CL
226 busaddr = raddr;
227 /* rotate to correct position */
5989b2f5
CL
228 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
229 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
230 /* select byte or word */
231 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
666ceb03 232 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
2bcc55d5 233 data_size = insn[22] ? 3'b001 : 3'b100;
5989b2f5
CL
234 case(lsr_state)
235 2'b01: begin
236 rd_req = insn[20];
237 wr_req = ~insn[20];
666ceb03
CL
238 next_write_reg = 1'b1;
239 next_write_num = insn[15:12];
5989b2f5 240 if(insn[20]) begin
5989b2f5 241 next_write_data = align_rddata;
a02ca509 242 end
666ceb03 243 if(insn[21] | !insn[24]) begin
5989b2f5
CL
244 outstall = 1'b1;
245 if(!rw_wait)
246 next_lsr_state = 2'b10;
a02ca509 247 end
d73619a2 248 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
b3bb2fb8 249 end
5989b2f5
CL
250 2'b10: begin
251 next_write_reg = 1'b1;
252 next_write_num = insn[19:16];
253 next_write_data = addr;
feb2b5be 254 next_lsr_state = 2'b01;
5989b2f5
CL
255 end
256 default: begin end
257 endcase
b3bb2fb8 258 end
5989b2f5
CL
259 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
260 `DECODE_LDMSTM: if(!inbubble) begin
9a0d0e43
CL
261 outstall = rw_wait;
262 next_outbubble = rw_wait;
2bcc55d5 263 data_size = 3'b100;
9a0d0e43
CL
264 case(lsm_state)
265 3'b001: begin
b114e03f
CL
266// next_regs = insn[23] ? op1[15:0] : op1[0:15];
267 /** verilator can suck my dick */
b957d34d
JW
268 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
269 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
270 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
b114e03f 271 offset = 6'b0;
9a0d0e43
CL
272 outstall = 1'b1;
273 next_lsm_state = 3'b010;
e08b748a 274 end
9a0d0e43
CL
275 3'b010: begin
276 rd_req = insn[20];
277 wr_req = ~insn[20];
9f082c0b
CL
278 casez(regs)
279 16'b???????????????1: begin
e08b748a 280 cur_reg = 4'h0;
b114e03f 281 next_regs = {regs[15:1], 1'b0};
9f082c0b
CL
282 end
283 16'b??????????????10: begin
e08b748a 284 cur_reg = 4'h1;
b114e03f 285 next_regs = {regs[15:2], 2'b0};
9f082c0b
CL
286 end
287 16'b?????????????100: begin
e08b748a 288 cur_reg = 4'h2;
b114e03f 289 next_regs = {regs[15:3], 3'b0};
9f082c0b
CL
290 end
291 16'b????????????1000: begin
e08b748a 292 cur_reg = 4'h3;
b114e03f 293 next_regs = {regs[15:4], 4'b0};
9f082c0b
CL
294 end
295 16'b???????????10000: begin
e08b748a 296 cur_reg = 4'h4;
b114e03f 297 next_regs = {regs[15:5], 5'b0};
9f082c0b
CL
298 end
299 16'b??????????100000: begin
e08b748a 300 cur_reg = 4'h5;
b114e03f 301 next_regs = {regs[15:6], 6'b0};
9f082c0b
CL
302 end
303 16'b?????????1000000: begin
e08b748a 304 cur_reg = 4'h6;
b114e03f 305 next_regs = {regs[15:7], 7'b0};
9f082c0b
CL
306 end
307 16'b????????10000000: begin
e08b748a 308 cur_reg = 4'h7;
b114e03f 309 next_regs = {regs[15:8], 8'b0};
9f082c0b
CL
310 end
311 16'b???????100000000: begin
e08b748a 312 cur_reg = 4'h8;
b114e03f 313 next_regs = {regs[15:9], 9'b0};
9f082c0b
CL
314 end
315 16'b??????1000000000: begin
e08b748a 316 cur_reg = 4'h9;
b114e03f 317 next_regs = {regs[15:10], 10'b0};
9f082c0b
CL
318 end
319 16'b?????10000000000: begin
e08b748a 320 cur_reg = 4'hA;
b114e03f 321 next_regs = {regs[15:11], 11'b0};
9f082c0b
CL
322 end
323 16'b????100000000000: begin
e08b748a 324 cur_reg = 4'hB;
b114e03f 325 next_regs = {regs[15:12], 12'b0};
9f082c0b
CL
326 end
327 16'b???1000000000000: begin
e08b748a 328 cur_reg = 4'hC;
b114e03f 329 next_regs = {regs[15:13], 13'b0};
9f082c0b
CL
330 end
331 16'b??10000000000000: begin
e08b748a 332 cur_reg = 4'hD;
b114e03f 333 next_regs = {regs[15:14], 14'b0};
9f082c0b
CL
334 end
335 16'b?100000000000000: begin
e08b748a 336 cur_reg = 4'hE;
b114e03f 337 next_regs = {regs[15], 15'b0};
9f082c0b
CL
338 end
339 16'b1000000000000000: begin
e08b748a 340 cur_reg = 4'hF;
9f082c0b
CL
341 next_regs = 16'b0;
342 end
343 default: begin
e08b748a
CL
344 cur_reg = 4'hx;
345 next_regs = 16'b0;
9f082c0b
CL
346 end
347 endcase
b957d34d 348 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
efd1aa13
CL
349 if(cur_reg == 4'hF && insn[22]) begin
350 next_outcpsr = spsr;
351 end
b114e03f 352
95704fd3 353 offset = prev_offset + 6'h4;
d73619a2
JW
354 offset_sel = insn[24] ? offset : prev_offset;
355 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
356 if(insn[20]) begin
357 next_write_reg = !rw_wait;
358 next_write_num = cur_reg;
359 next_write_data = rd_data;
360 end
361 if (rw_wait) begin
362 next_regs = regs;
363 cur_reg = prev_reg; /* whoops, do this one again */
b114e03f
CL
364 end
365
366 st_read = cur_reg;
b957d34d 367 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
666ceb03 368 busaddr = raddr;
b957d34d 369
d73619a2 370 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
9a0d0e43
CL
371
372 outstall = 1'b1;
373
374 if(next_regs == 16'b0) begin
375 next_lsm_state = 3'b100;
376 end
377 end
378 3'b100: begin
b957d34d 379 next_write_reg = insn[21] /* writeback */;
9a0d0e43
CL
380 next_write_num = insn[19:16];
381 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
382 next_lsm_state = 3'b001;
d73619a2 383 $display("LDMSTM: Stage 3: Writing back");
b783a475 384 end
d73619a2 385 default: $stop;
9a0d0e43 386 endcase
d73619a2 387 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
b3bb2fb8 388 end
5989b2f5 389 `DECODE_LDCSTC: if(!inbubble) begin
43e4332c
JW
390 $display("WARNING: Unimplemented LDCSTC");
391 end
5989b2f5 392 `DECODE_CDP: if(!inbubble) begin
43e4332c
JW
393 cp_req = 1;
394 if (cp_busy) begin
395 outstall = 1;
396 next_outbubble = 1;
397 end
398 if (!cp_ack) begin
399 /* XXX undefined instruction trap */
400 $display("WARNING: Possible CDP undefined instruction");
401 end
402 end
5989b2f5 403 `DECODE_MRCMCR: if(!inbubble) begin
43e4332c
JW
404 cp_req = 1;
405 cp_rnw = insn[20] /* L */;
406 if (insn[20] == 0 /* store to coprocessor */)
407 cp_write = op0;
408 else begin
d1d0eb8e
JW
409 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
410 next_write_reg = 1'b1;
411 next_write_num = insn[15:12];
412 next_write_data = cp_read;
413 end else
414 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
43e4332c
JW
415 end
416 if (cp_busy) begin
417 outstall = 1;
418 next_outbubble = 1;
419 end
420 if (!cp_ack) begin
838e283e 421 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
43e4332c 422 end
838e283e 423 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
43e4332c 424 end
b3bb2fb8
CL
425 default: begin end
426 endcase
d73619a2
JW
427
428 if ((flush || delayedflush) && !outstall)
429 next_outbubble = 1'b1;
b3bb2fb8 430 end
b3bb2fb8 431endmodule
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