DCache: Clear out a rw_wait reference in a $display that caused Verilator to throw...
[firearm.git] / ICache.v
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1/* 16 cache entries, 64-byte long cache lines */
2
3module ICache(
4 input clk,
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5
6 /* ARM core interface */
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7 input [31:0] rd_addr,
8 input rd_req,
9 output reg rd_wait,
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10 output reg [31:0] rd_data,
11
12 /* bus interface */
90ff449a 13 output wire bus_req,
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14 input bus_ack,
15 output reg [31:0] bus_addr,
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16 input [31:0] bus_rdata,
17 output wire [31:0] bus_wdata,
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18 output reg bus_rd,
19 output wire bus_wr,
20 input bus_ready);
21
22 assign bus_wr = 0;
cb1e103e 23 assign bus_wdata = 0;
7e757d70 24
f83818d5 25 /* [31 tag 10] [9 cache index 6] [5 data index 0]
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26 * so the data index is 6 bits long
27 * so the cache index is 4 bits long
f83818d5 28 * so the tag is 22 bits long. c.c
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29 */
30
31 reg cache_valid [15:0];
f83818d5 32 reg [21:0] cache_tags [15:0];
2b5c79c0 33 reg [31:0] cache_data [255:0 /* {line, word} */]; //synthesis attribute ram_style of cache_data is distributed
7e757d70 34
4dc31744 35 integer i;
7e757d70 36 initial
cb1e103e 37 for (i = 0; i < 16; i = i + 1)
90ff449a 38 begin
cb1e103e 39 cache_valid[i[3:0]] = 0;
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40 cache_tags[i[3:0]] = 0;
41 end
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42
43 wire [5:0] rd_didx = rd_addr[5:0];
44 wire [3:0] rd_didx_word = rd_didx[5:2];
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45 wire [3:0] rd_idx = rd_addr[9:6];
46 wire [21:0] rd_tag = rd_addr[31:10];
7e757d70 47
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48 reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
49
c808669d 50 wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
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51
52 reg [3:0] cache_fill_pos = 0;
45fa96c0 53 assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
28c904cc 54 always @(*)
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55 if (rd_req && !cache_hit && bus_ack) begin
56 bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
57 bus_rd = 1;
327f45ff 58 end else begin
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59 bus_addr = 0;
60 bus_rd = 0;
61 end
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62
63 wire [31:0] curdata = cache_data[{rd_idx,rd_didx_word}];
64 always @(*) begin
65 rd_wait = rd_req && !cache_hit;
66 rd_data = curdata;
67 end
327f45ff 68
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69 always @(posedge clk) begin
70 prev_rd_addr <= {rd_addr[31:6], 6'b0};
71 if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
72 cache_fill_pos <= 0;
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73 else if (rd_req && !cache_hit && bus_ack && bus_ready) begin
74 $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
75 cache_data[{rd_idx,cache_fill_pos}] <= bus_rdata;
76 cache_fill_pos <= cache_fill_pos + 1;
77 if (cache_fill_pos == 15) begin /* Done? */
78 cache_tags[rd_idx] <= rd_tag;
79 cache_valid[rd_idx] <= 1;
80 $display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
81 end else
82 cache_valid[rd_idx] <= 0;
c808669d 83 end
8b417b45 84 end
7e757d70 85endmodule
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