some work on cache filling, and fleshing out a bus interface
[firearm.git] / icache.v
CommitLineData
7e757d70
JW
1/* 16 cache entries, 64-byte long cache lines */
2
3module ICache(
4 input clk,
c808669d
JW
5
6 /* ARM core interface */
7e757d70
JW
7 input [31:0] rd_addr,
8 input rd_req,
9 output reg rd_wait,
c808669d
JW
10 output reg [31:0] rd_data,
11
12 /* bus interface */
13 output reg bus_req,
14 input bus_ack,
15 output reg [31:0] bus_addr,
16 input [31:0] bus_data
17 output reg bus_rd,
18 output wire bus_wr,
19 input bus_ready);
20
21 assign bus_wr = 0;
7e757d70 22
f83818d5 23 /* [31 tag 10] [9 cache index 6] [5 data index 0]
7e757d70
JW
24 * so the data index is 6 bits long
25 * so the cache index is 4 bits long
f83818d5 26 * so the tag is 22 bits long. c.c
7e757d70
JW
27 */
28
29 reg cache_valid [15:0];
f83818d5 30 reg [21:0] cache_tags [15:0];
7e757d70
JW
31 reg [31:0] cache_data [15:0] [7:0];
32
33 initial
34 for (i = 0; i < 16; i = i + 1)
35 cache_valid[i] <= 0;
36
37 wire [5:0] rd_didx = rd_addr[5:0];
38 wire [3:0] rd_didx_word = rd_didx[5:2];
f83818d5
JW
39 wire [3:0] rd_idx = rd_addr[9:6];
40 wire [21:0] rd_tag = rd_addr[31:10];
7e757d70 41
c808669d
JW
42 wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
43
7e757d70 44 always @(*) begin /* XXX does this work nowadays? */
c808669d 45 rd_wait = !cache_hit;
7e757d70
JW
46 rd_data = cache_data[rd_idx][rd_didx_word];
47 end
c808669d
JW
48
49 reg [3:0] cache_fill_pos = 0;
50 reg cache_filling = 0;
51 always @(*) begin
52 if (!cache_hit) begin
53 bus_req = 1;
54 if (bus_ack) begin
55 bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
56 bus_rd = 1;
57 end
58 end
7e757d70 59endmodule
This page took 0.024831 seconds and 4 git commands to generate.