Memory: Move coprocessor and register outputs to their own always blocks.
[firearm.git] / Fetch.v
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1module Fetch(
2 input clk,
3 input Nrst,
4
5 output wire [31:0] rd_addr,
6 output wire rd_req,
7 input rd_wait,
8 input [31:0] rd_data,
9
10 input stall,
11 input jmp,
45fa96c0 12 input [31:0] jmppc,
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13 output reg bubble = 1,
14 output reg [31:0] insn = 0,
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15 output reg [31:0] pc = 32'hFFFFFFFC);
16
ac3ae95a 17 reg qjmp = 0; /* A jump has been queued up while we were waiting. */
6318a7e8 18 reg [31:0] qjmppc;
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19 always @(posedge clk or negedge Nrst)
20 if (!Nrst)
21 qjmp <= 0;
22 else if ((rd_wait || stall) && jmp)
6318a7e8 23 {qjmp,qjmppc} <= {jmp, jmppc};
ae185fc4 24 else if (!rd_wait && !stall && qjmp) /* It has already been intoed. */
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25 {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
26
27 reg [31:0] reqpc;
28 always @(*)
29 if (stall)
30 reqpc = pc;
31 else if (qjmp)
32 reqpc = qjmppc;
bd073175 33 else if (jmp)
6318a7e8 34 reqpc = jmppc;
bd073175 35 else
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36 reqpc = pc + 4;
37
38 assign rd_addr = reqpc;
39 assign rd_req = 1;
40
d43b0ab9 41 always @(posedge clk or negedge Nrst)
90ff449a 42 begin
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43 if (!Nrst) begin
44 pc <= 32'hFFFFFFFC;
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45 bubble <= 1;
46 end else if (!stall)
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47 begin
48 bubble <= rd_wait;
49 insn <= rd_data;
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50 if (!rd_wait)
51 pc <= reqpc;
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52 end
53 end
bd073175 54endmodule
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