Memory: Move coprocessor and register outputs to their own always blocks.
[firearm.git] / Fetch.v
1 module Fetch(
2         input clk,
3         input Nrst,
4         
5         output wire [31:0] rd_addr,
6         output wire rd_req,
7         input rd_wait,
8         input [31:0] rd_data,
9         
10         input stall,
11         input jmp,
12         input [31:0] jmppc,
13         output reg bubble = 1,
14         output reg [31:0] insn = 0,
15         output reg [31:0] pc = 32'hFFFFFFFC);
16         
17         reg qjmp = 0;   /* A jump has been queued up while we were waiting. */
18         reg [31:0] qjmppc;
19         always @(posedge clk or negedge Nrst)
20                 if (!Nrst)
21                         qjmp <= 0;
22                 else if ((rd_wait || stall) && jmp)
23                         {qjmp,qjmppc} <= {jmp, jmppc};
24                 else if (!rd_wait && !stall && qjmp)    /* It has already been intoed. */
25                         {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
26         
27         reg [31:0] reqpc;
28         always @(*)
29                 if (stall)
30                         reqpc = pc;
31                 else if (qjmp)
32                         reqpc = qjmppc;
33                 else if (jmp)
34                         reqpc = jmppc;
35                 else
36                         reqpc = pc + 4;
37         
38         assign rd_addr = reqpc;
39         assign rd_req = 1;
40         
41         always @(posedge clk or negedge Nrst)
42         begin
43                 if (!Nrst) begin
44                         pc <= 32'hFFFFFFFC;
45                         bubble <= 1;
46                 end else if (!stall)
47                 begin
48                         bubble <= rd_wait;
49                         insn <= rd_data;
50                         if (!rd_wait)
51                                 pc <= reqpc;
52                 end
53         end
54 endmodule
This page took 0.020641 seconds and 4 git commands to generate.