Wire up a display.

diff --git a/VTerm.v b/VTerm.v
index 62591bf012576d7dc93bf9e3b2a0cfa57328503e..2bf17787bd3341a1a7b8e37dae835016328be38b 100644 (file)
--- a/VTerm.v
+++ b/VTerm.v
@@ -49,10 +49,28 @@ module VTerm(
 
        SyncGen sync(clk25, vs, hs, x, y, border);
        
+       wire [7:0] cschar;
+       wire [2:0] csrow;
+       wire [7:0] csdata;
+       
+       wire [11:0] vraddr;
+       wire [7:0] vrdata;
+       
+       reg [11:0] vwaddr = 0;
+       
+       wire odata;
+       
+       CharSet cs(cschar, csrow, csdata);
+       VideoRAM vram(clk25, vraddr, vrdata, vwaddr, 8'h41, 1);
+       VDisplay dpy(clk25, x, y, vraddr, vrdata, cschar, csrow, csdata, odata);
+       
+       always @(posedge clk25)
+               vwaddr <= vwaddr + 1;
+       
        always @(posedge clk25) begin
-               red <= border ? 0 : 3'b100;
-               green <= border ? 0 : 0;
-               blue <= border ? 0 : 0;
+               red <= border ? 0 : {3{odata}};
+               green <= border ? 0 : {3{odata}};
+               blue <= border ? 0 : {2{odata}};
        end
 endmodule
 
@@ -88,3 +106,62 @@ module SyncGen(
                border <= (x > XRES) || (y > YRES);
        end
 endmodule
+
+module CharSet(
+       input [7:0] char,
+       input [2:0] row,
+       output wire [7:0] data);
+
+       reg [7:0] rom [(256 * 8 - 1):0];
+       
+       initial
+               $readmemb("ibmpc1.mem", rom);
+
+       assign data = rom[{char, row}];
+endmodule
+
+module VideoRAM(
+       input pixclk,
+       input [11:0] raddr,
+       output reg [7:0] rdata,
+       input [11:0] waddr,
+       input [7:0] wdata,
+       input wr);
+       
+       reg [7:0] ram [80*25-1 : 0];
+       
+       always @(posedge pixclk)
+               rdata <= ram[raddr];
+       
+       always @(posedge pixclk)
+               if (wr)
+                       ram[waddr] <= wdata;
+endmodule
+
+module VDisplay(
+       input pixclk,
+       input [11:0] x,
+       input [11:0] y,
+       output wire [11:0] raddr,
+       input [7:0] rchar,
+       output wire [7:0] cschar,
+       output wire [2:0] csrow,
+       input [7:0] csdata,
+       output reg data
+       );
+
+       wire [7:0] col = x[11:3];
+       wire [5:0] row = y[9:3];
+       reg [7:0] ch;
+       reg [11:0] xdly;
+
+       assign raddr = ({row,4'b0} + {row,6'b0} + {4'h0,col});
+       assign cschar = rchar;
+       assign csrow = y[2:0];
+       
+       always @(posedge pixclk)
+               xdly <= x;
+       
+       always @(posedge pixclk)
+               data = ((xdly < 80 * 8) && (y < 25 * 8)) ? csdata[7 - xdly[2:0]] : 0;
+endmodule