#define ICH2_SMI_STS_LEGACY_USB_STS (1 << 3)
#define ICH2_SMI_STS_BIOS_STS (1 << 2)
+#define ICH2_PMBASE_MON_SMI 0x40
+#define ICH2_MON_SMI_DEV7_TRAP_STS (1 << 15)
+#define ICH2_MON_SMI_DEV6_TRAP_STS (1 << 14)
+#define ICH2_MON_SMI_DEV5_TRAP_STS (1 << 13)
+#define ICH2_MON_SMI_DEV4_TRAP_STS (1 << 12)
+#define ICH2_MON_SMI_DEV7_TRAP_EN (1 << 11)
+#define ICH2_MON_SMI_DEV6_TRAP_EN (1 << 10)
+#define ICH2_MON_SMI_DEV5_TRAP_EN (1 << 9)
+#define ICH2_MON_SMI_DEV4_TRAP_EN (1 << 8)
+
+#define ICH2_PMBASE_DEVACT_STS 0x44
+#define ICH2_DEVACT_STS_ADLIB_ACT_STS (1 << 13)
+#define ICH2_DEVACT_STS_KBC_ACT_STS (1 << 12)
+#define ICH2_DEVACT_STS_MIDI_ACT_STS (1 << 11)
+#define ICH2_DEVACT_STS_AUDIO_ACT_STS (1 << 10)
+#define ICH2_DEVACT_STS_PIRQDH_ACT_STS (1 << 9)
+#define ICH2_DEVACT_STS_PIRQCG_ACT_STS (1 << 8)
+#define ICH2_DEVACT_STS_PIRQBF_ACT_STS (1 << 7)
+#define ICH2_DEVACT_STS_PIRQAE_ACT_STS (1 << 6)
+#define ICH2_DEVACT_STS_LEG_ACT_STS (1 << 5)
+#define ICH2_DEVACT_STS_IDES1_ACT_STS (1 << 3)
+#define ICH2_DEVACT_STS_IDES0_ACT_STS (1 << 2)
+#define ICH2_DEVACT_STS_IDEP1_ACT_STS (1 << 1)
+#define ICH2_DEVACT_STS_IDEP0_ACT_STS (1 << 0)
+
+#define ICH2_PMBASE_DEVTRAP_EN 0x48
+#define ICH2_DEVTRAP_EN_ADLIB_TRP_EN (1 << 13)
+#define ICH2_DEVTRAP_EN_KBC_TRP_EN (1 << 12)
+#define ICH2_DEVTRAP_EN_MIDI_TRP_EN (1 << 11)
+#define ICH2_DEVTRAP_EN_AUDIO_TRP_EN (1 << 10)
+#define ICH2_DEVTRAP_EN_LEG_TRP_EN (1 << 5)
+#define ICH2_DEVTRAP_EN_IDES1_TRP_EN (1 << 3)
+#define ICH2_DEVTRAP_EN_IDES0_TRP_EN (1 << 2)
+#define ICH2_DEVTRAP_EN_IDEP1_TRP_EN (1 << 1)
+#define ICH2_DEVTRAP_EN_IDEP0_TRP_EN (1 << 0)
+
#define ICH2_IDE_BUS 0
#define ICH2_IDE_DEV 31
#define ICH2_IDE_FN 1