outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
}
if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
}
if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
}
if (sts & ICH2_SMI_STS_SLP_SMI_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
}
if (sts & ICH2_SMI_STS_SLP_SMI_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
}
if (sts & ICH2_SMI_STS_APM_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
}
if (sts & ICH2_SMI_STS_APM_STS)
{
outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
}
if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
{
outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
}
if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
{
outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
}
if (pm1_sts & ICH2_PM1_STS_GBL_STS)
{
outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
}
if (pm1_sts & ICH2_PM1_STS_GBL_STS)
{
outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
}
if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
{
outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
}
if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
{
unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
}
if (sts & ICH2_SMI_STS_PERIODIC_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
}
if (sts & ICH2_SMI_STS_PERIODIC_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
}
if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
}
if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
}
if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
}
if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
{
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
}
if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG) /* Either the chipset is buggy, or we are. */
outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
}
if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG) /* Either the chipset is buggy, or we are. */
outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |