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1#ifndef _REG_82801B_H
2#define _REG_82801B_H
3
4#define ICH2_PCI_BRIDGE_BUS 0
5#define ICH2_PCI_BRIDGE_DEV 30
6#define ICH2_PCI_BRIDGE_FN 0
7
8#define ICH2_NIC_BUS 1
9#define ICH2_NIC_DEV 8
10#define ICH2_NIC_FN 0
11
12#define ICH2_LPC_BUS 0
13#define ICH2_LPC_DEV 31
14#define ICH2_LPC_FN 0
15
16#define ICH2_LPC_PCI_PMBASE 0x40
17#define ICH2_PMBASE_MASK 0xFF80
18#define ICH2_LPC_PCI_ACPI_CTRL 0x44
19#define ICH2_LPC_PCI_GPIOBASE 0x58
20#define ICH2_LPC_PCI_GPIO_CNTL 0x5C
21#define ICH2_LPC_PCI_GEN_PMCON1 0xA0
22#define ICH2_LPC_PCI_GEN_PMCON2 0xA2
23#define ICH2_LPC_PCI_GEN_PMCON3 0xA4
24#define ICH2_LPC_PCI_GPI_ROUT 0xB8
25#define ICH2_LPC_PCI_TRP_FWD_EN 0xC0
26#define ICH2_LPC_PCI_MON4_TRP_RNG 0xC4
27#define ICH2_LPC_PCI_MON5_TRP_RNG 0xC6
28#define ICH2_LPC_PCI_MON6_TRP_RNG 0xC8
29#define ICH2_LPC_PCI_MON7_TRP_RNG 0xCA
30#define ICH2_LPC_PCI_MON_TRP_MSK 0xCC
31
32#define ICH2_PMBASE_PM1_STS 0x00
33#define ICH2_PM1_STS_WAK_STS (1 << 15)
34#define ICH2_PM1_STS_PRBTNOR_STS (1 << 11)
35#define ICH2_PM1_STS_RTC_STS (1 << 10)
36#define ICH2_PM1_STS_PWRBTN_STS (1 << 8)
37#define ICH2_PM1_STS_GBL_STS (1 << 5)
38#define ICH2_PM1_STS_BM_STS (1 << 4)
39#define ICH2_PM1_STS_TMROF_STS (1 << 0)
40
41#define ICH2_PMBASE_PM1_EN 0x02
42#define ICH2_PM1_EN_RTC_EN (1 << 10)
43#define ICH2_PM1_EN_PWRBTN_EN (1 << 8)
44#define ICH2_PM1_EN_GBL_EN (1 << 5)
45#define ICH2_PM1_EN_TMROF_EN (1 << 0
46
47#define ICH2_PMBASE_PM1_TMR 0x08
48#define ICH2_PM1_TMR_FREQ 3579545 /* This will be the encryption key for a question on the test. */
49
50#define ICH2_PMBASE_SMI_EN 0x30
51#define ICH2_SMI_EN_PERIODIC_EN (1 << 14)
52#define ICH2_SMI_EN_TCO_EN (1 << 13)
53#define ICH2_SMI_EN_MCSMI_EN (1 << 11)
54#define ICH2_SMI_EN_BIOS_RLS (1 << 7)
55#define ICH2_SMI_EN_SWSMI_TMR_EN (1 << 6)
56#define ICH2_SMI_EN_APMC_EN (1 << 5)
57#define ICH2_SMI_EN_SLP_SMI_EN (1 << 4)
58#define ICH2_SMI_EN_LEGACY_USB_EN (1 << 3)
59#define ICH2_SMI_EN_BIOS_EN (1 << 2)
60#define ICH2_SMI_EN_EOS (1 << 1)
61#define ICH2_SMI_EN_GBL_SMI_EN (1 << 0)
62
63#define ICH2_PMBASE_SMI_STS 0x34
64#define ICH2_SMI_STS_SMBUS_SMI_STS (1 << 16)
65#define ICH2_SMI_STS_SERIRQ_SMI_STS (1 << 15)
66#define ICH2_SMI_STS_PERIODIC_STS (1 << 14)
67#define ICH2_SMI_STS_TCO_STS (1 << 13)
68#define ICH2_SMI_STS_DEVMON_STS (1 << 12)
69#define ICH2_SMI_STS_MCSMI_STS (1 << 11)
70#define ICH2_SMI_STS_GPE1_STS (1 << 10)
71#define ICH2_SMI_STS_GPE0_STS (1 << 9)
72#define ICH2_SMI_STS_PM1_STS_REG (1 << 8)
73#define ICH2_SMI_STS_SWSMI_TMR_STS (1 << 6)
74#define ICH2_SMI_STS_APM_STS (1 << 5)
75#define ICH2_SMI_STS_SLP_SMI_STS (1 << 4)
76#define ICH2_SMI_STS_LEGACY_USB_STS (1 << 3)
77#define ICH2_SMI_STS_BIOS_STS (1 << 2)
78
79#define ICH2_PMBASE_MON_SMI 0x40
80#define ICH2_MON_SMI_DEV7_TRAP_STS (1 << 15)
81#define ICH2_MON_SMI_DEV6_TRAP_STS (1 << 14)
82#define ICH2_MON_SMI_DEV5_TRAP_STS (1 << 13)
83#define ICH2_MON_SMI_DEV4_TRAP_STS (1 << 12)
84#define ICH2_MON_SMI_DEV7_TRAP_EN (1 << 11)
85#define ICH2_MON_SMI_DEV6_TRAP_EN (1 << 10)
86#define ICH2_MON_SMI_DEV5_TRAP_EN (1 << 9)
87#define ICH2_MON_SMI_DEV4_TRAP_EN (1 << 8)
88
89#define ICH2_PMBASE_DEVACT_STS 0x44
90#define ICH2_DEVACT_STS_ADLIB_ACT_STS (1 << 13)
91#define ICH2_DEVACT_STS_KBC_ACT_STS (1 << 12)
92#define ICH2_DEVACT_STS_MIDI_ACT_STS (1 << 11)
93#define ICH2_DEVACT_STS_AUDIO_ACT_STS (1 << 10)
94#define ICH2_DEVACT_STS_PIRQDH_ACT_STS (1 << 9)
95#define ICH2_DEVACT_STS_PIRQCG_ACT_STS (1 << 8)
96#define ICH2_DEVACT_STS_PIRQBF_ACT_STS (1 << 7)
97#define ICH2_DEVACT_STS_PIRQAE_ACT_STS (1 << 6)
98#define ICH2_DEVACT_STS_LEG_ACT_STS (1 << 5)
99#define ICH2_DEVACT_STS_IDES1_ACT_STS (1 << 3)
100#define ICH2_DEVACT_STS_IDES0_ACT_STS (1 << 2)
101#define ICH2_DEVACT_STS_IDEP1_ACT_STS (1 << 1)
102#define ICH2_DEVACT_STS_IDEP0_ACT_STS (1 << 0)
103
104#define ICH2_PMBASE_DEVTRAP_EN 0x48
105#define ICH2_DEVTRAP_EN_ADLIB_TRP_EN (1 << 13)
106#define ICH2_DEVTRAP_EN_KBC_TRP_EN (1 << 12)
107#define ICH2_DEVTRAP_EN_MIDI_TRP_EN (1 << 11)
108#define ICH2_DEVTRAP_EN_AUDIO_TRP_EN (1 << 10)
109#define ICH2_DEVTRAP_EN_LEG_TRP_EN (1 << 5)
110#define ICH2_DEVTRAP_EN_IDES1_TRP_EN (1 << 3)
111#define ICH2_DEVTRAP_EN_IDES0_TRP_EN (1 << 2)
112#define ICH2_DEVTRAP_EN_IDEP1_TRP_EN (1 << 1)
113#define ICH2_DEVTRAP_EN_IDEP0_TRP_EN (1 << 0)
114
115#define ICH2_IDE_BUS 0
116#define ICH2_IDE_DEV 31
117#define ICH2_IDE_FN 1
118
119#define ICH2_USB0_BUS 0
120#define ICH2_USB0_DEV 31
121#define ICH2_USB0_FN 2
122
123#define ICH2_USB1_BUS 0
124#define ICH2_USB1_DEV 31
125#define ICH2_USB1_FN 4
126
127#define ICH2_SMBUS_BUS 0
128#define ICH2_SMBUS_DEV 31
129#define ICH2_SMBUS_FN 3
130
131#define ICH2_AC97AUD_BUS 0
132#define ICH2_AC97AUD_DEV 31
133#define ICH2_AC97AUD_FN 5
134
135#define ICH2_AC97MOD_BUS 0
136#define ICH2_AC97MOD_DEV 31
137#define ICH2_AC97MOD_FN 6
138
139#endif
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