]> Joshua Wise's Git repositories - netwatch.git/blame - ich2/smram-ich2.c
second arg of memcpy should be const
[netwatch.git] / ich2 / smram-ich2.c
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99970893 1#include "reg-82815.h"
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2#include <pci.h>
3#include <smram.h>
99970893 4
c34aba05 5#ifndef __RAW__
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6
7static unsigned long memsz[] = {
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8 0, // 0
9 32*1024*1024, // 1
10 32*1024*1024, // 2
11 48*1024*1024, // 3
12 64*1024*1024, // 4
13 64*1024*1024, // 5
14 96*1024*1024, // 6
15 128*1024*1024, // 7
16 128*1024*1024, // 8
17 128*1024*1024, // 9
18 128*1024*1024, // A
19 192*1024*1024, // B
20 256*1024*1024, // C
21 256*1024*1024, // D
22 256*1024*1024, // E
23 512*1024*1024 // F
24};
25
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26void smram_aseg_dump(void) {
27
28 unsigned char smramc, drp, drp2;
29 unsigned int tom = 0;
30 int usmm, lsmm;
31
32 smramc = pci_read8(0, 0, 0, SMRAMC);
33 drp = pci_read8(0, 0, 0, DRP);
34 drp2 = pci_read8(0, 0, 0, DRP2);
35
36 printf("SMRAMC: %02x\n", smramc);
37
38 tom += memsz[drp & 0xF];
39 tom += memsz[drp >> 4];
40 tom += memsz[drp2 & 0xF];
41
42 printf("Top of DRAM: %08x\n", tom);
43
44 usmm = (smramc >> 4) & 0x3;
45 lsmm = (smramc >> 2) & 0x3;
46
47 switch (usmm)
48 {
49 case 0:
50 printf("TSEG and HSEG both off\n");
51 break;
52 case 1:
53 printf("TSEG off, HSEG %s\n", lsmm ? "off" : "on");
54 break;
55 case 2:
56 printf("TSEG 512KB (%08x - %08x), HSEG %s\n",
57 tom - 512 * 1024, tom - 1, lsmm ? "off" : "on");
58 break;
59 case 3:
60 printf("TSEG 1MB (%08x - %08x), HSEG %s\n",
61 tom - 1 * 1024 * 1024, tom - 1, lsmm ? "off" : "on");
62 break;
63 }
64
65 switch (lsmm)
66 {
67 case 0:
68 printf("ABSEG disabled\n");
69 break;
70 case 1:
71 printf("ABSEG enabled as system RAM\n");
72 break;
73 case 2:
74 printf("ABSEG enabled for SMM code only\n");
75 break;
76 case 3:
77 printf("ABSEG enabled for both SMM code and data\n");
78 break;
79 }
80}
81#endif
82
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83int smram_locked()
84{
85 unsigned char smramc = pci_read8(0, 0, 0, SMRAMC);
86
87 return (smramc & SMRAMC_LOCK) ? 1 : 0;
88}
89
90smram_state_t smram_save_state()
91{
92 return pci_read8(0, 0, 0, SMRAMC);
93}
94
95void smram_restore_state(smram_state_t state)
96{
36ce375d 97 pci_write8(0, 0, 0, SMRAMC, state);
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98}
99
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100int smram_aseg_set_state (int open) {
101 unsigned char smramc;
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102
103 if (smram_locked())
104 return -1;
105
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106 smramc = pci_read8(0, 0, 0, SMRAMC);
107
81148fa1 108 switch (open)
99970893 109 {
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110 case SMRAM_ASEG_CLOSED:
111 smramc = (smramc & 0xF0) | 0x00;
112 break;
113 case SMRAM_ASEG_OPEN:
99970893 114 smramc = (smramc & 0xF0) | 0x04;
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115 break;
116 case SMRAM_ASEG_SMMCODE:
117 smramc = (smramc & 0xF0) | 0x08;
118 break;
119 case SMRAM_ASEG_SMMONLY:
99970893 120 smramc = (smramc & 0xF0) | 0x0C;
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121 break;
122 default:
123 return -1;
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124 }
125
81148fa1 126 pci_write8(0, 0, 0, SMRAMC, smramc);
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127
128 return 0;
129}
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130
131int smram_tseg_set_state (int open) {
132 unsigned char smramc;
133
134 if (smram_locked())
135 return -1;
136
137 smramc = pci_read8(0, 0, 0, SMRAMC);
138
139 switch (open)
140 {
141 case SMRAM_TSEG_OPEN:
142 smramc = (smramc & 0x8F) | 0x00;
143 break;
144 default:
145 return -1;
146 }
147
148 pci_write8(0, 0, 0, SMRAMC, smramc);
149
150 return 0;
151}
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