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Optimization baseline, 77.788MHz, 4894 Slices, 1849 slice FFs, 9078 LUTs
[mandelfpga.git] / shnasto.cmd
1 setMode -bs
2 setCable -port svf -file "/home/joshua/projects/fpga/MandelFPGA/test.svf"
3 addDevice -p 1 -file "/home/joshua/projects/fpga/MandelFPGA/MandelTop.bit"
4 addDevice -p 2 -part xcf04s
5 Program -p 1 -defaultVersion 0
6 quit
7
Pipelined realtime renderer of the Mandelbrot set on a Xilinx FPGA
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