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Joshua Wise's Git repositories - fpgaboy.git/log
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Joshua Wise [Tue, 1 Apr 2008 07:47:54 +0000 (03:47 -0400)]
Poke the UART with a stick.
ABABABABABABAB
Joshua Wise [Tue, 1 Apr 2008 07:26:08 +0000 (03:26 -0400)]
Fix not-taken jumps. Add more ALU ops. Add ALU A ops.
Joshua Wise [Tue, 1 Apr 2008 07:18:26 +0000 (03:18 -0400)]
Test JP and JP cc
Joshua Wise [Tue, 1 Apr 2008 05:26:45 +0000 (01:26 -0400)]
JP
Joshua Wise [Tue, 1 Apr 2008 03:58:32 +0000 (23:58 -0400)]
Spit lots of A out of the UART.
Joshua Wise [Tue, 1 Apr 2008 03:14:16 +0000 (23:14 -0400)]
Get it running on the board.
Joshua Wise [Mon, 31 Mar 2008 11:09:14 +0000 (07:09 -0400)]
HALP ABOUT TO BLOW AWY PROJECT
Joshua Wise [Mon, 31 Mar 2008 06:58:27 +0000 (02:58 -0400)]
Fix RAM bugs with kludge. Fix CALL bug. CALL test case.
Joshua Wise [Mon, 31 Mar 2008 06:22:45 +0000 (02:22 -0400)]
Add CALL (untested) and ROM and internal RAM
Joshua Wise [Mon, 31 Mar 2008 03:46:49 +0000 (23:46 -0400)]
Fix part of the indentation tragedy.
Joshua Wise [Mon, 31 Mar 2008 03:34:09 +0000 (23:34 -0400)]
Add RET/IRET. Fix a bug in RST where the PC pushed to the stack was incorrect.
Joshua Wise [Mon, 31 Mar 2008 00:23:36 +0000 (20:23 -0400)]
RST insn
Joshua Wise [Sun, 30 Mar 2008 10:33:25 +0000 (06:33 -0400)]
NOP, and bug fixes
Joshua Wise [Sun, 30 Mar 2008 10:28:24 +0000 (06:28 -0400)]
Test XOR
Joshua Wise [Sun, 30 Mar 2008 10:04:28 +0000 (06:04 -0400)]
ADC, AND, OR, XOR
Joshua Wise [Sun, 30 Mar 2008 09:42:47 +0000 (05:42 -0400)]
Our first ALU operation -- ADD
Joshua Wise [Sun, 30 Mar 2008 07:41:07 +0000 (03:41 -0400)]
LD{D,I} A,(HL) and LD{D,I} (HL),A
Joshua Wise [Sun, 30 Mar 2008 07:06:08 +0000 (03:06 -0400)]
LDH A,(C) and LDH (C), A
Joshua Wise [Sat, 29 Mar 2008 08:22:48 +0000 (04:22 -0400)]
Add UCF for the z80 core
Joshua Wise [Sat, 29 Mar 2008 08:22:15 +0000 (04:22 -0400)]
update ISE project
Joshua Wise [Sat, 29 Mar 2008 08:15:58 +0000 (04:15 -0400)]
Make it synthesizable.
Joshua Wise [Sat, 29 Mar 2008 08:12:10 +0000 (04:12 -0400)]
PUSH and POP work
Joshua Wise [Sat, 29 Mar 2008 07:42:26 +0000 (03:42 -0400)]
LD reg, imm16 and LD SP,HL
Joshua Wise [Sat, 29 Mar 2008 06:46:01 +0000 (02:46 -0400)]
LD with HLs
Joshua Wise [Sat, 29 Mar 2008 06:24:43 +0000 (02:24 -0400)]
LD reg, reg
Joshua Wise [Sat, 29 Mar 2008 05:36:50 +0000 (01:36 -0400)]
Initial
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