RST insn
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 31 Mar 2008 00:23:36 +0000 (20:23 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 31 Mar 2008 00:23:36 +0000 (20:23 -0400)
FPGABoy.ise
GBZ80Core.v
rom.hex

index 2e6073a..8260443 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
index 3e15ebf..75f9722 100644 (file)
@@ -34,6 +34,7 @@
 `define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
 `define INSN_NOP                               8'b00000000
+`define INSN_RST                               8'b11xxx111
 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
@@ -338,6 +339,26 @@ module GBZ80Core(
                                `EXEC_NEWCYCLE;
                                `EXEC_INC_PC;
                        end
+                       `INSN_RST: begin
+                               case (cycle)
+                               0: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               wdata <= registers[`REG_PCH];
+                                       end
+                               1: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                               wdata <= registers[`REG_PCL];
+                                       end
+                               2:      begin /* wee */ end
+                               3: begin
+                                               `EXEC_NEWCYCLE;
+                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                                       {10'b0,opcode[5:3],3'b0};
+                                       end
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase
@@ -563,6 +584,18 @@ module GBZ80Core(
                                end
                        end
                        `INSN_NOP: begin /* NOP! */ end
+                       `INSN_RST: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      cycle <= 2;
+                               2: cycle <= 3;
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                       end
+                               endcase
+                       end
                        endcase
                        state <= `STATE_FETCH;
                end
diff --git a/rom.hex b/rom.hex
index a465631..b54409e 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -20,8 +20,8 @@ C1
 A8
 // LD (HL), A
 77
-// HALT
-76
+// RST 00h
+C7
 
 @100
 02
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