Fix part of the indentation tragedy.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 31 Mar 2008 03:46:49 +0000 (23:46 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 31 Mar 2008 03:46:49 +0000 (23:46 -0400)
FPGABoy.ise
GBZ80Core.v

index 491bbb3..50f4b03 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
index c0c2b26..338c2d7 100644 (file)
@@ -146,7 +146,7 @@ module GBZ80Core(
                                                `EXEC_NEXTADDR_PCINC;
                                                rd <= 1;
                                        end
-                               1: begin
+                               1:      begin
                                                `EXEC_INC_PC;
                                                if (opcode[5:3] == `INSN_reg_dHL) begin
                                                        address <= {registers[`REG_H], registers[`REG_L]};
@@ -157,7 +157,7 @@ module GBZ80Core(
                                                        `EXEC_NEWCYCLE;
                                                end
                                        end
-                               2: begin
+                               2:      begin
                                                `EXEC_NEWCYCLE;
                                        end
                                endcase
@@ -170,13 +170,13 @@ module GBZ80Core(
                                case (cycle)
                                0:      begin
                                                case (opcode[2:0])
-                                               `INSN_reg_A:    begin wdata <= registers[`REG_A]; end
-                                               `INSN_reg_B:    begin wdata <= registers[`REG_B]; end
-                                               `INSN_reg_C:    begin wdata <= registers[`REG_C]; end
-                                               `INSN_reg_D:    begin wdata <= registers[`REG_D]; end
-                                               `INSN_reg_E:    begin wdata <= registers[`REG_E]; end
-                                               `INSN_reg_H:    begin wdata <= registers[`REG_H]; end
-                                               `INSN_reg_L:    begin wdata <= registers[`REG_L]; end
+                                               `INSN_reg_A:    wdata <= registers[`REG_A];
+                                               `INSN_reg_B:    wdata <= registers[`REG_B];
+                                               `INSN_reg_C:    wdata <= registers[`REG_C];
+                                               `INSN_reg_D:    wdata <= registers[`REG_D];
+                                               `INSN_reg_E:    wdata <= registers[`REG_E];
+                                               `INSN_reg_H:    wdata <= registers[`REG_H];
+                                               `INSN_reg_L:    wdata <= registers[`REG_L];
                                                endcase
                                                address <= {registers[`REG_H], registers[`REG_L]};
                                                wr <= 1; rd <= 0;
@@ -189,11 +189,11 @@ module GBZ80Core(
                        end
                        `INSN_LD_reg_HL: begin
                                case(cycle)
-                               0: begin
+                               0:      begin
                                                address <= {registers[`REG_H], registers[`REG_L]};
                                                rd <= 1;
                                        end
-                               1: begin
+                               1:      begin
                                                tmp <= rdata;
                                                `EXEC_INC_PC;
                                                `EXEC_NEWCYCLE;
@@ -204,13 +204,13 @@ module GBZ80Core(
                                `EXEC_INC_PC;
                                `EXEC_NEWCYCLE;
                                case (opcode[2:0])
-                               `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
-                               `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
-                               `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
-                               `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
-                               `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
-                               `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
-                               `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
+                               `INSN_reg_A:    tmp <= registers[`REG_A];
+                               `INSN_reg_B:    tmp <= registers[`REG_B];
+                               `INSN_reg_C:    tmp <= registers[`REG_C];
+                               `INSN_reg_D:    tmp <= registers[`REG_D];
+                               `INSN_reg_E:    tmp <= registers[`REG_E];
+                               `INSN_reg_H:    tmp <= registers[`REG_H];
+                               `INSN_reg_L:    tmp <= registers[`REG_L];
                                endcase
                        end
                        `INSN_LD_reg_imm16: begin
@@ -241,7 +241,7 @@ module GBZ80Core(
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
-                               0: begin
+                               0:      begin
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                case (opcode[5:4])
@@ -251,7 +251,7 @@ module GBZ80Core(
                                                `INSN_stack_HL: wdata <= registers[`REG_H];
                                                endcase
                                        end
-                               1: begin
+                               1:      begin
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                case (opcode[5:4])
@@ -262,7 +262,7 @@ module GBZ80Core(
                                                endcase
                                        end
                                2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
-                               3: begin
+                               3:      begin
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end
@@ -270,15 +270,15 @@ module GBZ80Core(
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)
-                               0: begin
+                               0:      begin
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end
-                               1: begin
+                               1:      begin
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end
-                               2: begin
+                               2:      begin
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end
@@ -295,7 +295,7 @@ module GBZ80Core(
                                                        wdata <= registers[`REG_A];
                                                end
                                        end
-                               1: begin
+                               1:      begin
                                                `EXEC_NEWCYCLE;
                                                `EXEC_INC_PC;
                                        end
@@ -303,7 +303,7 @@ module GBZ80Core(
                        end
                        `INSN_LDx_AHL: begin
                                case (cycle)
-                               0: begin
+                               0:      begin
                                                address <= {registers[`REG_H],registers[`REG_L]};
                                                if (opcode[3]) begin    // LDx A, (HL)
                                                        rd <= 1;
@@ -327,14 +327,14 @@ module GBZ80Core(
                                        `EXEC_NEWCYCLE;
                                        `EXEC_INC_PC;
                                        case (opcode[2:0])
-                                       `INSN_reg_A:    begin tmp <= registers[`REG_A]; end
-                                       `INSN_reg_B:    begin tmp <= registers[`REG_B]; end
-                                       `INSN_reg_C:    begin tmp <= registers[`REG_C]; end
-                                       `INSN_reg_D:    begin tmp <= registers[`REG_D]; end
-                                       `INSN_reg_E:    begin tmp <= registers[`REG_E]; end
-                                       `INSN_reg_H:    begin tmp <= registers[`REG_H]; end
-                                       `INSN_reg_L:    begin tmp <= registers[`REG_L]; end
-                                       `INSN_reg_dHL:  begin tmp <= rdata; end
+                                       `INSN_reg_A:    tmp <= registers[`REG_A];
+                                       `INSN_reg_B:    tmp <= registers[`REG_B];
+                                       `INSN_reg_C:    tmp <= registers[`REG_C];
+                                       `INSN_reg_D:    tmp <= registers[`REG_D];
+                                       `INSN_reg_E:    tmp <= registers[`REG_E];
+                                       `INSN_reg_H:    tmp <= registers[`REG_H];
+                                       `INSN_reg_L:    tmp <= registers[`REG_L];
+                                       `INSN_reg_dHL:  tmp <= rdata;
                                        endcase
                                end
                        end
@@ -345,19 +345,19 @@ module GBZ80Core(
                        `INSN_RST: begin
                                case (cycle)
                                0:      begin
-                                               `EXEC_INC_PC;           // This goes FIRST
+                                               `EXEC_INC_PC;           // This goes FIRST in RST
                                        end
-                               1: begin
+                               1:      begin
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
                                                wdata <= registers[`REG_PCH];
                                        end
-                               2: begin
+                               2:      begin
                                                wr <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                                wdata <= registers[`REG_PCL];
                                        end
-                               3: begin
+                               3:      begin
                                                `EXEC_NEWCYCLE;
                                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                                        {10'b0,opcode[5:3],3'b0};
@@ -390,8 +390,8 @@ module GBZ80Core(
                        casex (opcode)
                        `INSN_LD_reg_imm8:
                                case (cycle)
-                               0: cycle <= 1;
-                               1: case (opcode[5:3])
+                               0:      cycle <= 1;
+                               1:      case (opcode[5:3])
                                        `INSN_reg_A:    begin registers[`REG_A] <= rdata; cycle <= 0; end
                                        `INSN_reg_B:    begin registers[`REG_B] <= rdata; cycle <= 0; end
                                        `INSN_reg_C:    begin registers[`REG_C] <= rdata; cycle <= 0; end
@@ -401,7 +401,7 @@ module GBZ80Core(
                                        `INSN_reg_L:    begin registers[`REG_L] <= rdata; cycle <= 0; end
                                        `INSN_reg_dHL:  cycle <= 2;
                                        endcase
-                               2: cycle <= 0;
+                               2:      cycle <= 0;
                                endcase
                        `INSN_HALT: begin
                                /* Nothing needs happen here. */
@@ -409,8 +409,8 @@ module GBZ80Core(
                        end
                        `INSN_LD_HL_reg: begin
                                case (cycle)
-                               0: cycle <= 1;
-                               1: cycle <= 0;
+                               0:      cycle <= 1;
+                               1:      cycle <= 0;
                                endcase
                        end
                        `INSN_LD_reg_HL: begin
@@ -418,13 +418,13 @@ module GBZ80Core(
                                0:      cycle <= 1;
                                1:      begin
                                                case (opcode[5:3])
-                                               `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
-                                               `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
-                                               `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
-                                               `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
-                                               `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
-                                               `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
-                                               `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                                               `INSN_reg_L:    registers[`REG_L] <= tmp;
                                                endcase
                                                cycle <= 0;
                                        end
@@ -432,13 +432,13 @@ module GBZ80Core(
                        end
                        `INSN_LD_reg_reg: begin
                                case (opcode[5:3])
-                               `INSN_reg_A:    begin registers[`REG_A] <= tmp; end
-                               `INSN_reg_B:    begin registers[`REG_B] <= tmp; end
-                               `INSN_reg_C:    begin registers[`REG_C] <= tmp; end
-                               `INSN_reg_D:    begin registers[`REG_D] <= tmp; end
-                               `INSN_reg_E:    begin registers[`REG_E] <= tmp; end
-                               `INSN_reg_H:    begin registers[`REG_H] <= tmp; end
-                               `INSN_reg_L:    begin registers[`REG_L] <= tmp; end
+                               `INSN_reg_A:    registers[`REG_A] <= tmp;
+                               `INSN_reg_B:    registers[`REG_B] <= tmp;
+                               `INSN_reg_C:    registers[`REG_C] <= tmp;
+                               `INSN_reg_D:    registers[`REG_D] <= tmp;
+                               `INSN_reg_E:    registers[`REG_E] <= tmp;
+                               `INSN_reg_H:    registers[`REG_H] <= tmp;
+                               `INSN_reg_L:    registers[`REG_L] <= tmp;
                                endcase
                        end
                        `INSN_LD_reg_imm16: begin
@@ -610,7 +610,7 @@ module GBZ80Core(
                                case (cycle)
                                0:      cycle <= 1;
                                1:      cycle <= 2;
-                               2: cycle <= 3;
+                               2:      cycle <= 3;
                                3:      begin
                                                cycle <= 0;
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
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