Clean up some warnings.

diff --git a/GBZ80Core.v b/GBZ80Core.v
index b53a6e20ec07a736baa0452c971e2d060c5ea8e2..d556cd50cd5eb81cc1398616df0418bdc7f34390 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -90,9 +90,9 @@
 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,

-       output reg [15:0] busaddress = 0,       /* BUS_* is latched on STATE_FETCH. */
+       output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */

        inout [7:0] busdata,
        inout [7:0] busdata,

-       output reg buswr = 0, output reg busrd = 0,
+       output reg buswr, output reg busrd,

        input irq, input [7:0] jaddr);
        
        reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
        input irq, input [7:0] jaddr);
        
        reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */


@@ -112,7 +112,7 @@ module GBZ80Core(
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        

-       reg ie = 0, iedelay = 0;
+       reg ie, iedelay;

        
        initial begin
                registers[ 0] <= 0;
        
        initial begin
                registers[ 0] <= 0;

diff --git a/System.v b/System.v
index 5d4fbedf2acadf14bd48a28dfb153570ed63a1cf..0afc09066159f17645bd92537eab33fc43f5f908 100644 (file)
--- a/System.v
+++ b/System.v
@@ -26,7 +26,6 @@ module InternalRAM(
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;

-       wire idata = data;

        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)


@@ -97,12 +96,11 @@ module CoreTop(
                .rd(rd));
        
        AddrMon amon(
                .rd(rd));
        
        AddrMon amon(

-    .addr(addr), 
-    .clk(clk), 
-    .digit(digits), 
-    .out(seven),
-        .freeze(buttons[0])
-    );
+               .addr(addr), 
+               .clk(clk), 
+               .digit(digits), 
+               .out(seven),
+               .freeze(buttons[0]));

         
        Switches sw(
                .address(addr),
         
        Switches sw(
                .address(addr),


@@ -115,20 +113,21 @@ module CoreTop(
                );
 
        UART nouart (   /* no u */
                );
 
        UART nouart (   /* no u */

-    .clk(clk), 
-    .wr(wr), 
-    .rd(rd), 
-    .addr(addr), 
-    .data(data), 
-    .serial(serio)
-    );
+               .clk(clk), 
+               .wr(wr), 
+               .rd(rd), 
+               .addr(addr), 
+               .data(data), 
+               .serial(serio)
+               );

 
 

-  InternalRAM ram(
+       InternalRAM ram(

                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),

-               .rd(rd));
+               .rd(rd)
+               );

 
        Timer tmr(
                .clk(clk),
 
        Timer tmr(
                .clk(clk),


@@ -136,7 +135,8 @@ module CoreTop(
                .rd(rd),
                .addr(addr),
                .data(data),
                .rd(rd),
                .addr(addr),
                .data(data),

-               .irq(tmrirq));
+               .irq(tmrirq)
+               );

        
        Interrupt intr(
                .clk(clk),
        
        Interrupt intr(
                .clk(clk),

diff --git a/Uart.v b/Uart.v
index f87005dfc2aaa9b0b5af9fc322acec14a78c5c2f..3dd15323fd012ee5d9357038989790776f919bfc 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -19,7 +19,6 @@ module UART(
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
        reg have_data = 0;
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
        reg have_data = 0;

-       reg data_end = 0;

        reg [3:0] diqing = 4'b0000;
        
        wire new = (wr) && (!have_data) && decode;
        reg [3:0] diqing = 4'b0000;
        
        wire new = (wr) && (!have_data) && decode;