Move macro defines out to files

diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index 053df4a1a4619c6a8eaf7a220ff21d6bd9418f3a..fcc3337e13b2244aa4d423fae5a3c3faa81c21e0 100644 (file)
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -40,46 +40,9 @@
 `define STATE_EXECUTE          2'h2
 `define STATE_WRITEBACK                2'h3
 
-`define INSN_LD_reg_imm8       9'b000xxx110
-`define INSN_HALT              9'b001110110
-`define INSN_LD_HL_reg         9'b001110xxx
-`define INSN_LD_reg_HL         9'b001xxx110
-`define INSN_LD_reg_reg                9'b001xxxxxx
-`define INSN_LD_reg_imm16      9'b000xx0001
-`define INSN_LD_SP_HL          9'b011111001
-`define INSN_PUSH_reg          9'b011xx0101
-`define INSN_POP_reg           9'b011xx0001
-`define INSN_LDH_AC            9'b0111x0010    // Either LDH A,(C) or LDH (C),A
-`define INSN_LDx_AHL           9'b0001xx010    // LDD/LDI A,(HL) / (HL),A
-`define INSN_ALU8              9'b010xxxxxx    // 10 xxx yyy
-`define INSN_ALU8IMM           9'b011xxx110
-`define INSN_NOP               9'b000000000
-`define INSN_RST               9'b011xxx111
-`define INSN_RET               9'b0110x1001    // 1 = RETI, 0 = RET
-`define INSN_RETCC             9'b0110xx000
-`define INSN_CALL              9'b011001101
-`define INSN_CALLCC            9'b0110xx100    // Not that call/cc.
-`define INSN_JP_imm            9'b011000011
-`define INSN_JPCC_imm          9'b0110xx010
-`define INSN_ALU_A             9'b000xxx111
-`define INSN_JP_HL             9'b011101001
-`define INSN_JR_imm            9'b000011000
-`define INSN_JRCC_imm          9'b0001xx000
-`define INSN_INCDEC16          9'b000xxx011
 `define INSN_VOP_INTR          9'b011111100    // 0xFC is grabbed by the fetch if there is an interrupt pending.
-`define INSN_DI                        9'b011110011
-`define INSN_EI                        9'b011111011
-`define INSN_INCDEC_HL         9'b00011010x
-`define INSN_INCDEC_reg8       9'b000xxx10x
-`define INSN_LD8M_A            9'b0111x0000    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
-`define INSN_LD16M_A           9'b0111x1010    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
-`define INSN_LDBCDE_A          9'b0000xx010
-`define INSN_TWO_BYTE          9'b011001011    // prefix for two-byte opqodes
-`define INSN_ALU_EXT           9'b100xxxxxx
-`define INSN_BIT               9'b101xxxxxx
 `define INSN_RES               9'b110xxxxxx
 `define INSN_SET               9'b111xxxxxx
-`define INSN_ADD_HL            9'b000xx1001
 
 `define INSN_cc_NZ             2'b00
 `define INSN_cc_Z              2'b01
@@ -110,14 +73,6 @@
 `define INSN_alu_XOR           3'b101
 `define INSN_alu_OR            3'b110
 `define INSN_alu_CP            3'b111          // Oh lawd, is dat some CP?
-`define INSN_alu_RLCA          3'b000
-`define INSN_alu_RRCA          3'b001
-`define INSN_alu_RLA           3'b010
-`define INSN_alu_RRA           3'b011
-`define INSN_alu_DAA           3'b100
-`define INSN_alu_CPL           3'b101
-`define INSN_alu_SCF           3'b110
-`define INSN_alu_CCF           3'b111
 `define INSN_alu_RLC           3'b000
 `define INSN_alu_RRC           3'b001
 `define INSN_alu_RL            3'b010
@@ -131,18 +86,13 @@
 `define EXEC_NEXTADDR_PCINC    address <= `_PC + 1;
 `define EXEC_NEWCYCLE          begin newcycle <= 1; rd <= 1; wr <= 0; end
 `define EXEC_NEWCYCLE_TWOBYTE  begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
-`ifdef verilator
+`ifdef isim
        `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
        `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
 `else
-       `ifdef isim
-               `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
-               `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
-       `else
-/* Work around XST's retarded bugs :\ */
-               `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
-               `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
-       `endif
+       /* Work around XST's retarded bugs :\ */
+       `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
+       `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
 `endif
 
 module GBZ80Core(

diff --git a/core/insn_add_hl.v b/core/insn_add_hl.v
index 8ff25f46b00b11b49f1f19e547146359c1e1fb2d..0d85f953f5713ec704c696b927a4018094d96a55 100644 (file)
--- a/core/insn_add_hl.v
+++ b/core/insn_add_hl.v
@@ -1,3 +1,5 @@
+`define INSN_ADD_HL            9'b000xx1001
+
 `ifdef EXECUTE
        `INSN_ADD_HL: begin
                case (cycle)

diff --git a/core/insn_alu8.v b/core/insn_alu8.v
index 2921b1858a3e9fdffe1b001557e3527a8e3886c4..1283a9cfbc5c00645c79c1bf65fa78dd3271216e 100644 (file)
--- a/core/insn_alu8.v
+++ b/core/insn_alu8.v
@@ -1,3 +1,6 @@
+`define INSN_ALU8              9'b010xxxxxx    // 10 xxx yyy
+`define INSN_ALU8IMM           9'b011xxx110
+
 `ifdef EXECUTE
        `INSN_ALU8,`INSN_ALU8IMM: begin
                if ((opcode[7:6] == 2'b11) && (cycle == 0)) begin       // alu8imm

diff --git a/core/insn_alu_a.v b/core/insn_alu_a.v
index 57a74fc9d71cb6f4c488251db7810f642583afde..14ccd76aae620ee90b99b6d54a463859e24d12af 100644 (file)
--- a/core/insn_alu_a.v
+++ b/core/insn_alu_a.v
@@ -1,3 +1,14 @@
+`define INSN_alu_RLCA          3'b000
+`define INSN_alu_RRCA          3'b001
+`define INSN_alu_RLA           3'b010
+`define INSN_alu_RRA           3'b011
+`define INSN_alu_DAA           3'b100
+`define INSN_alu_CPL           3'b101
+`define INSN_alu_SCF           3'b110
+`define INSN_alu_CCF           3'b111
+
+`define INSN_ALU_A             9'b000xxx111
+
 `ifdef EXECUTE
        `INSN_ALU_A: begin
                `EXEC_NEWCYCLE

diff --git a/core/insn_alu_ext.v b/core/insn_alu_ext.v
index 1b7825bda50dcc08df68c9f0e103e8dc13835a78..b4046e80c48316bf7179c0a0aea9b6227f91068f 100644 (file)
--- a/core/insn_alu_ext.v
+++ b/core/insn_alu_ext.v
@@ -1,3 +1,5 @@
+`define INSN_ALU_EXT           9'b100xxxxxx
+
 `ifdef EXECUTE
        `INSN_ALU_EXT: begin
                if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
@@ -24,6 +26,7 @@
                        if(cycle == 0) begin end
                        else if(cycle == 1) begin
                                `EXEC_WRITE(`_HL, alu_res)
+                               `_F <= {f_res,`_F[3:0]};
                        end else begin
                                `EXEC_NEWCYCLE
                        end

diff --git a/core/insn_bit.v b/core/insn_bit.v
index 379215e2314728844e1ca8be3ffff0610c9ccf79..ca50e58c2524319919d5be14405f54737a94d535 100644 (file)
--- a/core/insn_bit.v
+++ b/core/insn_bit.v
@@ -1,3 +1,5 @@
+`define INSN_BIT               9'b101xxxxxx
+
 `ifdef EXECUTE
        `INSN_BIT: begin
                if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin

diff --git a/core/insn_call-callcc.v b/core/insn_call-callcc.v
index a446a3d07ac3cb61868c911759beebf0500120e5..85cea27897074ff5cd99943c8ce29cc1034d0da8 100644 (file)
--- a/core/insn_call-callcc.v
+++ b/core/insn_call-callcc.v
@@ -1,3 +1,6 @@
+`define INSN_CALL              9'b011001101
+`define INSN_CALLCC            9'b0110xx100    // Not that call/cc.
+
 `ifdef EXECUTE
        `INSN_CALL,`INSN_CALLCC: begin
                case (cycle)

diff --git a/core/insn_di-ei.v b/core/insn_di-ei.v
index eff1de25d4d60d426071cefea7d6bd1f918965ea..6e65ceb1e4e4aa56d4b1af1792497a08ba327976 100644 (file)
--- a/core/insn_di-ei.v
+++ b/core/insn_di-ei.v
@@ -1,3 +1,6 @@
+`define INSN_DI                        9'b011110011
+`define INSN_EI                        9'b011111011
+
 `ifdef EXECUTE
        `INSN_DI,`INSN_EI: begin
                `EXEC_NEWCYCLE

diff --git a/core/insn_halt.v b/core/insn_halt.v
index 4d2573fb91c3f9c80e2f29e451c42e7cf64835b7..9a3c1c025e36bf1775eec5ae1bfe13238e86183e 100644 (file)
--- a/core/insn_halt.v
+++ b/core/insn_halt.v
@@ -1,3 +1,5 @@
+`define INSN_HALT              9'b001110110
+
 `ifdef EXECUTE
        `INSN_HALT: begin
                `EXEC_NEWCYCLE

diff --git a/core/insn_incdec16.v b/core/insn_incdec16.v
index 95e0d3824d8399b73de395cc08ac79541843d8fa..14897794869e52098c7479c6744b8117edd1d533 100644 (file)
--- a/core/insn_incdec16.v
+++ b/core/insn_incdec16.v
@@ -1,3 +1,5 @@
+`define INSN_INCDEC16          9'b000xxx011
+
 `ifdef EXECUTE
        `INSN_INCDEC16: begin
                case (cycle)

diff --git a/core/insn_incdec_hl.v b/core/insn_incdec_hl.v
index abfe4952f6e21a42ca268d1564cb60806cb7b54f..1406fd8b9890e77a3ff7065663001c440ebd9954 100644 (file)
--- a/core/insn_incdec_hl.v
+++ b/core/insn_incdec_hl.v
@@ -1,3 +1,5 @@
+`define INSN_INCDEC_HL         9'b00011010x
+
 `ifdef EXECUTE
        `INSN_INCDEC_HL: begin
                case (cycle)

diff --git a/core/insn_incdec_reg8.v b/core/insn_incdec_reg8.v
index 58582b60dc9d00cb909061e063d682a9254f2339..e89ceba54d63903c91776137d37ba5df4b78e729 100644 (file)
--- a/core/insn_incdec_reg8.v
+++ b/core/insn_incdec_reg8.v
@@ -1,3 +1,5 @@
+`define INSN_INCDEC_reg8       9'b000xxx10x
+
 `ifdef EXECUTE
        `INSN_INCDEC_reg8: begin
                `EXEC_INC_PC

diff --git a/core/insn_jp-jpcc.v b/core/insn_jp-jpcc.v
index 7c8fb22efbf70a536c9e621367274d23c4ac3723..c54043d10ea127168f6de9a8c119a01744ef0ef5 100644 (file)
--- a/core/insn_jp-jpcc.v
+++ b/core/insn_jp-jpcc.v
@@ -1,3 +1,6 @@
+`define INSN_JP_imm            9'b011000011
+`define INSN_JPCC_imm          9'b0110xx010
+
 `ifdef EXECUTE
        `INSN_JP_imm,`INSN_JPCC_imm: begin
                case (cycle)

diff --git a/core/insn_jp_hl.v b/core/insn_jp_hl.v
index 4aa9a41748e62c4cf2a65f1383916b0a5ca47d9a..707f62c0e9ecad9acba03cfb77441305075a1fff 100644 (file)
--- a/core/insn_jp_hl.v
+++ b/core/insn_jp_hl.v
@@ -1,3 +1,5 @@
+`define INSN_JP_HL             9'b011101001
+
 `ifdef EXECUTE
        `INSN_JP_HL:    `EXEC_NEWCYCLE
 `endif

diff --git a/core/insn_jr-jrcc.v b/core/insn_jr-jrcc.v
index 767db6a7c0fb2bb1cfd7b69550cc79dbf94c2dc5..a2c5f7ebc815f8bc14deae007f99313ebc113e56 100644 (file)
--- a/core/insn_jr-jrcc.v
+++ b/core/insn_jr-jrcc.v
@@ -1,3 +1,6 @@
+`define INSN_JR_imm            9'b000011000
+`define INSN_JRCC_imm          9'b0001xx000
+
 `ifdef EXECUTE
        `INSN_JR_imm,`INSN_JRCC_imm: begin
                case (cycle)

diff --git a/core/insn_ld_hl_reg.v b/core/insn_ld_hl_reg.v
index fdf3d9ba0a27a7a17416503ef03f6d67d9a2f8e6..974584fde8f017371351fe644ca5843f24fd7435 100644 (file)
--- a/core/insn_ld_hl_reg.v
+++ b/core/insn_ld_hl_reg.v
@@ -1,3 +1,5 @@
+`define INSN_LD_HL_reg         9'b001110xxx
+
 `ifdef EXECUTE
        `INSN_LD_HL_reg: begin
                case (cycle)

diff --git a/core/insn_ld_reg_hl.v b/core/insn_ld_reg_hl.v
index e420f2ff37b35c7746f9484dff431bb5b716321f..f6a67c76f57b433b72fafe876de6add599f3867c 100644 (file)
--- a/core/insn_ld_reg_hl.v
+++ b/core/insn_ld_reg_hl.v
@@ -1,3 +1,5 @@
+`define INSN_LD_reg_HL         9'b001xxx110
+
 `ifdef EXECUTE
        `INSN_LD_reg_HL: begin
                case(cycle)

diff --git a/core/insn_ld_reg_imm16.v b/core/insn_ld_reg_imm16.v
index cf79aaab948f94e9d8727efb383df5144f30481f..3784fbf6c9b03c8d282015b03c942e681c0f370f 100644 (file)
--- a/core/insn_ld_reg_imm16.v
+++ b/core/insn_ld_reg_imm16.v
@@ -1,3 +1,5 @@
+`define INSN_LD_reg_imm16      9'b000xx0001
+
 `ifdef EXECUTE
        `INSN_LD_reg_imm16: begin
                `EXEC_INC_PC

diff --git a/core/insn_ld_reg_imm8.v b/core/insn_ld_reg_imm8.v
index 73404217ca77a4b8d35d0d2357db4222dc29c4e3..b1deb9c915b23939b75d8da68a2829e9164ce413 100644 (file)
--- a/core/insn_ld_reg_imm8.v
+++ b/core/insn_ld_reg_imm8.v
@@ -1,3 +1,5 @@
+`define INSN_LD_reg_imm8       9'b000xxx110
+
 `ifdef EXECUTE
        `INSN_LD_reg_imm8: begin
                case (cycle)

diff --git a/core/insn_ld_reg_reg.v b/core/insn_ld_reg_reg.v
index 7bbea9511647a10323b492197cd95452d4308f53..e0d72e7d40e9f320bf4baed289b4c2fc231635d0 100644 (file)
--- a/core/insn_ld_reg_reg.v
+++ b/core/insn_ld_reg_reg.v
@@ -1,3 +1,5 @@
+`define INSN_LD_reg_reg                9'b001xxxxxx
+
 `ifdef EXECUTE
        `INSN_LD_reg_reg: begin
                `EXEC_INC_PC

diff --git a/core/insn_ld_sp_hl.v b/core/insn_ld_sp_hl.v
index 3d4fc1846ba54dca0b1003534c6beb14e17e9f66..55546f80b423effa64f9562c9653b5938a0d15e0 100644 (file)
--- a/core/insn_ld_sp_hl.v
+++ b/core/insn_ld_sp_hl.v
@@ -1,3 +1,5 @@
+`define INSN_LD_SP_HL          9'b011111001
+
 `ifdef EXECUTE
        `INSN_LD_SP_HL: begin
                case (cycle)

diff --git a/core/insn_ldbcde_a.v b/core/insn_ldbcde_a.v
index 2a91dc65ebd060668515a1c75b6877246e6338c2..5ce0ee1f394e0503cf30e8ed275b814242107557 100644 (file)
--- a/core/insn_ldbcde_a.v
+++ b/core/insn_ldbcde_a.v
@@ -1,3 +1,5 @@
+`define INSN_LDBCDE_A          9'b0000xx010
+
 `ifdef EXECUTE
        `INSN_LDBCDE_A: begin
                case (cycle)

diff --git a/core/insn_ldh_ac.v b/core/insn_ldh_ac.v
index a2ff5cc1decce400b2494d9baa24532f0eec778b..30918e5c08ef4f7c1b4e0da54c993a42bf0ac0eb 100644 (file)
--- a/core/insn_ldh_ac.v
+++ b/core/insn_ldh_ac.v
@@ -1,3 +1,5 @@
+`define INSN_LDH_AC            9'b0111x0010    // Either LDH A,(C) or LDH (C),A
+
 `ifdef EXECUTE
        `INSN_LDH_AC: begin
                case (cycle)

diff --git a/core/insn_ldm16_a.v b/core/insn_ldm16_a.v
index d8356f76862a633a0fb3ae1bd76df27b3e8210b9..744551e7deb4b4a822d2511c240157c97e0af4e2 100644 (file)
--- a/core/insn_ldm16_a.v
+++ b/core/insn_ldm16_a.v
@@ -1,3 +1,5 @@
+`define INSN_LD16M_A           9'b0111x1010    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+
 // If opcode[4], then ld A, x, else ld x, A
 // If opcode[1], then ld 16m8, else ld 8m8
 

diff --git a/core/insn_ldm8_a.v b/core/insn_ldm8_a.v
index 14d82cae0551e95abb579e0cf3da6c0a2015d782..8a5ffa476e989fa1d1711f80d6fdce1d77663e1b 100644 (file)
--- a/core/insn_ldm8_a.v
+++ b/core/insn_ldm8_a.v
@@ -1,3 +1,5 @@
+`define INSN_LD8M_A            9'b0111x0000    // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+
 // If opcode[4], then ld A, x, else ld x, A
 // If opcode[1], then ld 16m8, else ld 8m8
 

diff --git a/core/insn_ldx_ahl.v b/core/insn_ldx_ahl.v
index a2d2420b166e74d556833ddd2503619d9a920649..55a8f2142b85437b01ce8d292d4282d720283514 100644 (file)
--- a/core/insn_ldx_ahl.v
+++ b/core/insn_ldx_ahl.v
@@ -1,3 +1,5 @@
+`define INSN_LDx_AHL           9'b0001xx010    // LDD/LDI A,(HL) / (HL),A
+
 `ifdef EXECUTE
        `INSN_LDx_AHL: begin
                case (cycle)

diff --git a/core/insn_nop.v b/core/insn_nop.v
index 9270c881acdbbd03d7082e850b9af20b30771b4b..d8ba833aece892c4c0a35898d072becc6baca13f 100644 (file)
--- a/core/insn_nop.v
+++ b/core/insn_nop.v
@@ -1,3 +1,5 @@
+`define INSN_NOP               9'b000000000
+
 `ifdef EXECUTE
        `INSN_NOP: begin
                `EXEC_NEWCYCLE

diff --git a/core/insn_pop_reg.v b/core/insn_pop_reg.v
index 5a7da08fcf6fb4cefe31fe26d5a48947089a45c9..55d12ece5331ceb8f0e4e82918c3ab4029ce2c08 100644 (file)
--- a/core/insn_pop_reg.v
+++ b/core/insn_pop_reg.v
@@ -1,3 +1,5 @@
+`define INSN_POP_reg           9'b011xx0001
+
 `ifdef EXECUTE
        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                case (cycle)

diff --git a/core/insn_push_reg.v b/core/insn_push_reg.v
index 6b789e54d933df3e397808d99f114412af3398bf..0c3692acb260911dc24ad5f2465cc04059a9ff3f 100644 (file)
--- a/core/insn_push_reg.v
+++ b/core/insn_push_reg.v
@@ -1,3 +1,5 @@
+`define INSN_PUSH_reg          9'b011xx0101
+
 `ifdef EXECUTE
        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                case (cycle)

diff --git a/core/insn_ret-retcc.v b/core/insn_ret-retcc.v
index dab27c3ef99023b050b109758daabe7dd44fa1af..4ad962eb4e0e0ff377fe2dce4e92a17a6eb61392 100644 (file)
--- a/core/insn_ret-retcc.v
+++ b/core/insn_ret-retcc.v
@@ -1,3 +1,6 @@
+`define INSN_RET               9'b0110x1001    // 1 = RETI, 0 = RET
+`define INSN_RETCC             9'b0110xx000
+
 `ifdef EXECUTE
        `INSN_RET,`INSN_RETCC: begin
                case (cycle)

diff --git a/core/insn_rst.v b/core/insn_rst.v
index 4b65032179092d8753d834e11e8aac232e706a4c..8ec0421e5279f17deec7dfce029ce16f41551a91 100644 (file)
--- a/core/insn_rst.v
+++ b/core/insn_rst.v
@@ -1,3 +1,5 @@
+`define INSN_RST               9'b011xxx111
+
 `ifdef EXECUTE
        `INSN_RST: begin
                case (cycle)

diff --git a/core/insn_two_byte.v b/core/insn_two_byte.v
index 78cd7c70396d8f14228f737ee527a775f67372f6..7a51cbc6f1908bbf5f692cdb8933824c5ff5e2eb 100644 (file)
--- a/core/insn_two_byte.v
+++ b/core/insn_two_byte.v
@@ -1,3 +1,5 @@
+`define INSN_TWO_BYTE          9'b011001011    // prefix for two-byte opqodes
+
 `ifdef EXECUTE
        `INSN_TWO_BYTE: begin
                `EXEC_INC_PC