Move macro defines out to files

[fpgaboy.git] / core / insn_alu_ext.v

`define INSN_ALU_EXT		9'b100xxxxxx

`ifdef EXECUTE
	`INSN_ALU_EXT: begin
		if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
			`EXEC_READ(`_HL)
		else begin
			`EXEC_INC_PC
			case (opcode[2:0])
			`INSN_reg_A:    tmp <= `_A;
			`INSN_reg_B:    tmp <= `_B;
			`INSN_reg_C:    tmp <= `_C;
			`INSN_reg_D:    tmp <= `_D;
			`INSN_reg_E:    tmp <= `_E;
			`INSN_reg_H:    tmp <= `_H;
			`INSN_reg_L:    tmp <= `_L;
			`INSN_reg_dHL:  tmp <= rdata;
			endcase
		end
	end
`endif

`ifdef WRITEBACK
	`INSN_ALU_EXT: begin
		if (opcode[2:0] == `INSN_reg_dHL) begin
			if(cycle == 0) begin end
			else if(cycle == 1) begin
				`EXEC_WRITE(`_HL, alu_res)
				`_F <= {f_res,`_F[3:0]};
			end else begin
				`EXEC_NEWCYCLE
			end
		end else begin
			case(opcode[2:0])
			`INSN_reg_B: `_B <= alu_res;
			`INSN_reg_C: `_C <= alu_res;
			`INSN_reg_D: `_D <= alu_res;
			`INSN_reg_E: `_E <= alu_res;
			`INSN_reg_H: `_H <= alu_res;
			`INSN_reg_L: `_L <= alu_res;
			`INSN_reg_A: `_A <= alu_res;
			`INSN_reg_dHL: begin end /* eat dicks */
			endcase
			`_F <= {f_res,`_F[3:0]};
			`EXEC_NEWCYCLE
		end
	end
`endif