-`define ADDR_P1 16'hFF10
+`define ADDR_P1 16'hFF00
/* note: buttons are 'pressed' when the input is high */
input rd,
input [15:0] addr,
inout [7:0] data,
- input [7:0] buttons
+ input [7:0] buttons,
output reg int
);
+ reg rdlatch;
+ reg [15:0] addrlatch;
+
reg [7:0] p1;
reg [3:0] oldp1013;
- assign data = (rd && (addr == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
+ assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
- wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
+ wire [3:0] p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) & (p1[5] ? 4'b1111 : ~buttons[7:4]);
- always @ (negedge core_clk) begin
+ always @ (posedge core_clk) begin
if(wr) begin
case(addr)
`ADDR_P1: p1[5:4] <= data[5:4];
endcase
end
+ rdlatch <= rd;
+ addrlatch <= addr;
p1[3:0] <= p1013;
oldp1013 <= p1013;
int <= | (oldp1013 & (oldp1013 ^ p1013));
verilog work "Sound1.v"
verilog work "Sound2.v"
verilog work "Soundcore.v"
+verilog work "Buttons.v"
VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
- Sound2.v Soundcore.v System.v Timer.v Uart.v
+ Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v
VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \
insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \
wire [7:0] data [1:0];
wire wr [1:0], rd [1:0];
- wire irq, tmrirq, lcdcirq, vblankirq;
+ wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
wire [7:0] jaddr;
wire [1:0] state;
wire ack;
.ledout(leds),
.switches(switches)
);
+
+ Buttons ass(
+ .core_clk(clk),
+ .addr(addr[0]),
+ .data(data[0]),
+ .wr(wr[0]),
+ .rd(rd[0]),
+ .int(btnirq),
+ .buttons(switches)
+ );
AddrMon amon(
.clk(clk),
.lcdc(lcdcirq),
.tovf(tmrirq),
.serial(1'b0),
- .buttons(1'b0),
+ .buttons(btnirq),
.master(irq),
.ack(ack),
.jaddr(jaddr));
void dowrite(char *s, int len)
{
- int i;
- for (i=0; i<len; i++)
+ int i = 0;
+ while (i < len)
{
- write(1, s+i, 1);
+ int cs = ((len-i) > 1) ? 1 : (len-i);
+
+ write(1, s+i, cs);
+ i += cs;
}
}