]> Joshua Wise's Git repositories - fpgaboy.git/blame - CoreTop.prj
Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / CoreTop.prj
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1verilog work "Uart.v"
2verilog work "Timer.v"
3verilog work "Interrupt.v"
4verilog work "GBZ80Core.v"
5verilog work "CPUDCM.v"
6verilog work "7seg.v"
7verilog work "System.v"
8verilog work "LCDC.v"
9verilog work "Framebuffer.v"
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10verilog work "pixDCM.v"
11verilog work "Sound1.v"
12verilog work "Sound2.v"
13verilog work "Soundcore.v"
a6b499da 14verilog work "Buttons.v"
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