DAA compile fixes, and PROGFLASH addr increment fix

diff --git a/System.v b/System.v
index e0baebe3c65f9dad345554cc8137b35010ed4282..f89b2a6538ade01a2052737eb15d59adfa3a1d5a 100644 (file)
--- a/System.v
+++ b/System.v
@@ -137,6 +137,10 @@ module CellularRAM(
                                        progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
                                        {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
                                end
+               ADDR_PROGFLASH: if (rd || wr) begin
+                                       progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
+                                       {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
+                               end
                ADDR_MBC:       begin
                                        mbc_emul <= data;
                                        rambank <= 0;

diff --git a/core/insn_alu_a.v b/core/insn_alu_a.v
index 80d317dc6b999216baa41d669296ce0b659c71e9..3d7e917b0a29154cd217a973fc0f86d280293131 100644 (file)
--- a/core/insn_alu_a.v
+++ b/core/insn_alu_a.v
@@ -38,7 +38,7 @@
                `INSN_alu_DAA: begin
                        if (`_F[6]) begin                               
                                if (`_F[4]) begin
-                                       if(`_A[3:0] >= 4'h6 && `_A[7:4] >= 4'h6 && `F[5]) begin
+                                       if(`_A[3:0] >= 4'h6 && `_A[7:4] >= 4'h6 && `_F[5]) begin
                                                `_A <= `_A + 8'h9A;
                                                `_F <= {((`_A + 8'h9A) == 8'b0), `_F[6:0]};
                                        end
@@ -63,7 +63,7 @@
                                                `_A <= `_A + 8'h66;
                                                `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]};
                                        end
-                                       else if (`_A[3:0] > 4'b9) begin
+                                       else if (`_A[3:0] > 4'h9) begin
                                                `_A <= `_A + 8'h66;
                                                `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]};
                                        end