Cut 1 at button integration
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 9 May 2008 10:03:18 +0000 (06:03 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 9 May 2008 10:03:18 +0000 (06:03 -0400)
Buttons.v
CoreTop.prj
Makefile
System.v
binwire.c

index 6caecd6..4d8a171 100644 (file)
--- a/Buttons.v
+++ b/Buttons.v
@@ -8,23 +8,28 @@ module Buttons(
        input rd,
        input [15:0] addr,
        inout [7:0] data,
-       input [7:0] buttons
+       input [7:0] buttons,
        output reg int
        );
 
+       reg rdlatch;
+       reg [15:0] addrlatch;
+
        reg [7:0] p1;
        reg [3:0] oldp1013;
 
-       assign data = (rd && (addr == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
+       assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
 
        wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(wr) begin
                        case(addr)
                        `ADDR_P1: p1[5:4] <= data[5:4];
                        endcase
                end
+               rdlatch <= rd;
+               addrlatch <= addr;
                p1[3:0] <= p1013;
                oldp1013 <= p1013;
                int <= | (oldp1013 & (oldp1013 ^ p1013));
index 2b334db..0df5890 100644 (file)
@@ -11,3 +11,4 @@ verilog work "pixDCM.v"
 verilog work "Sound1.v"
 verilog work "Sound2.v"
 verilog work "Soundcore.v"
+verilog work "Buttons.v"
index 40ea542..f42e5b9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
-       Sound2.v Soundcore.v System.v Timer.v Uart.v
+       Sound2.v Soundcore.v System.v Timer.v Uart.v  Buttons.v
 
 VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \
        insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \
index 62f976b..931e900 100644 (file)
--- a/System.v
+++ b/System.v
@@ -262,7 +262,7 @@ module CoreTop(
        wire [7:0] data [1:0];
        wire wr [1:0], rd [1:0];
        
-       wire irq, tmrirq, lcdcirq, vblankirq;
+       wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
        wire [7:0] jaddr;
        wire [1:0] state;
        wire ack;
@@ -357,6 +357,16 @@ module CoreTop(
                .ledout(leds),
                .switches(switches)
                );
+       
+       Buttons ass(
+               .core_clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .int(btnirq),
+               .buttons(switches)
+               );
 
        AddrMon amon(
                .clk(clk), 
@@ -415,7 +425,7 @@ module CoreTop(
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(1'b0),
-               .buttons(1'b0),
+               .buttons(btnirq),
                .master(irq),
                .ack(ack),
                .jaddr(jaddr));
index 101b5c1..cef0924 100644 (file)
--- a/binwire.c
+++ b/binwire.c
@@ -7,10 +7,13 @@
 
 void dowrite(char *s, int len)
 {
-  int i;
-  for (i=0; i<len; i++)
+  int i = 0;
+  while (i < len)
   {
-    write(1, s+i, 1);
+    int cs = ((len-i) > 1) ? 1 : (len-i);
+    
+    write(1, s+i, cs);
+    i += cs;
   }
 }
 
This page took 0.061785 seconds and 4 git commands to generate.