From a6b499da5fd2a834963cc05178e6b8044dc9129f Mon Sep 17 00:00:00 2001
From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Fri, 9 May 2008 06:03:18 -0400
Subject: [PATCH] Cut 1 at button integration

---
 Buttons.v   | 11 ++++++++---
 CoreTop.prj |  1 +
 Makefile    |  2 +-
 System.v    | 14 ++++++++++++--
 binwire.c   |  9 ++++++---
 5 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/Buttons.v b/Buttons.v
index 6caecd6..4d8a171 100644
--- a/Buttons.v
+++ b/Buttons.v
@@ -8,23 +8,28 @@ module Buttons(
 	input rd,
 	input [15:0] addr,
 	inout [7:0] data,
-	input [7:0] buttons
+	input [7:0] buttons,
 	output reg int
 	);
 
+	reg rdlatch;
+	reg [15:0] addrlatch;
+
 	reg [7:0] p1;
 	reg [3:0] oldp1013;
 
-	assign data = (rd && (addr == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
+	assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
 
 	wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
 
-	always @ (negedge core_clk) begin
+	always @ (posedge core_clk) begin
 		if(wr) begin
 			case(addr)
 			`ADDR_P1: p1[5:4] <= data[5:4];
 			endcase
 		end
+		rdlatch <= rd;
+		addrlatch <= addr;
 		p1[3:0] <= p1013;
 		oldp1013 <= p1013;
 		int <= | (oldp1013 & (oldp1013 ^ p1013));
diff --git a/CoreTop.prj b/CoreTop.prj
index 2b334db..0df5890 100644
--- a/CoreTop.prj
+++ b/CoreTop.prj
@@ -11,3 +11,4 @@ verilog work "pixDCM.v"
 verilog work "Sound1.v"
 verilog work "Sound2.v"
 verilog work "Soundcore.v"
+verilog work "Buttons.v"
diff --git a/Makefile b/Makefile
index 40ea542..f42e5b9 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
-	Sound2.v Soundcore.v System.v Timer.v Uart.v
+	Sound2.v Soundcore.v System.v Timer.v Uart.v  Buttons.v
 
 VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \
 	insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \
diff --git a/System.v b/System.v
index 62f976b..931e900 100644
--- a/System.v
+++ b/System.v
@@ -262,7 +262,7 @@ module CoreTop(
 	wire [7:0] data [1:0];
 	wire wr [1:0], rd [1:0];
 	
-	wire irq, tmrirq, lcdcirq, vblankirq;
+	wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
 	wire [7:0] jaddr;
 	wire [1:0] state;
 	wire ack;
@@ -357,6 +357,16 @@ module CoreTop(
 		.ledout(leds),
 		.switches(switches)
 		);
+	
+	Buttons ass(
+		.core_clk(clk),
+		.addr(addr[0]),
+		.data(data[0]),
+		.wr(wr[0]),
+		.rd(rd[0]),
+		.int(btnirq),
+		.buttons(switches)
+		);
 
 	AddrMon amon(
 		.clk(clk), 
@@ -415,7 +425,7 @@ module CoreTop(
 		.lcdc(lcdcirq),
 		.tovf(tmrirq),
 		.serial(1'b0),
-		.buttons(1'b0),
+		.buttons(btnirq),
 		.master(irq),
 		.ack(ack),
 		.jaddr(jaddr));
diff --git a/binwire.c b/binwire.c
index 101b5c1..cef0924 100644
--- a/binwire.c
+++ b/binwire.c
@@ -7,10 +7,13 @@
 
 void dowrite(char *s, int len)
 {
-  int i;
-  for (i=0; i<len; i++)
+  int i = 0;
+  while (i < len)
   {
-    write(1, s+i, 1);
+    int cs = ((len-i) > 1) ? 1 : (len-i);
+    
+    write(1, s+i, cs);
+    i += cs;
   }
 }
 
-- 
2.39.2