Test RAM

diff --git a/FPGABoy.ise b/FPGABoy.ise
index c429431d73867de7fbd4250bc3eaddf3a56a582b..aeefb4a09ec717488c88dedf33dd302c75bb7558 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/System.v b/System.v
index 259656abe330f3d4040723c7ed544401573c6c94..8fc4c9ca7d5ac8ed490cf86e6cb7214af0dd8046 100644 (file)
--- a/System.v
+++ b/System.v
@@ -23,7 +23,7 @@ module InternalRAM(
        
        reg [7:0] ram [8191:0];
        
-       wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+       wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
@@ -114,6 +114,13 @@ module CoreTop(
     .data(data), 
     .serial(serio)
     );
+
+  InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));
 endmodule
 
 module TestBench();
@@ -140,12 +147,12 @@ module TestBench();
                .wr(wr),
                .rd(rd));
        
-//     InternalRAM ram(
-//             .address(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd));
+       InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));
 
        wire serio;
        UART uart(

diff --git a/rom.hex b/rom.hex
index 504108d73fb2eac97236dadd745ccdb4e6ce6748..8ccdb424cc9f914e4d7c51f85cead6e6b22ca191 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -1,19 +1,18 @@
+31
+ff
+df
 0e
 50
 06
 00
-f2
-b8
-c2
-04
+cd
+16
 00
 3e
 41
 e2
-f2
-b8
-c2
-0c
+cd
+16
 00
 3e
 42
@@ -21,11 +20,12 @@ e2
 c3
 00
 00
+f2
+b8
+c2
+16
 00
-00
-00
-00
-00
+c9
 00
 00
 00