System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg [7:0] rom [2047:0];
  10         initial $readmemh("rom.hex", rom);
  11
  12         wire decode = address[15:13] == 0;
  13         wire [7:0] odata = rom[address[11:0]];
  14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  15         //assign data = rd ? odata : 8'bzzzzzzzz;
  16 endmodule
  17
  18 module InternalRAM(
  19         input [15:0] address,
  20         inout [7:0] data,
  21         input clk,
  22         input wr, rd);
  23
  24         reg [7:0] ram [8191:0];
  25
  26         wire decode = (address >= 16'hC000) && (address < 16'hFE00);
  27         reg [7:0] odata;
  28         wire idata = data;
  29         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  30
  31         always @(negedge clk)
  32         begin
  33                 if (decode && rd)
  34                         odata <= ram[address[12:0]];
  35                 else if (decode && wr)
  36                         ram[address[12:0]] <= data;
  37         end
  38 endmodule
  39
  40 module Switches(
  41         input [15:0] address,
  42         inout [7:0] data,
  43         input clk,
  44         input wr, rd,
  45         input [7:0] switches,
  46         output reg [7:0] ledout);
  47
  48         wire decode = address == 16'hFF51;
  49         reg [7:0] odata;
  50         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  51
  52         always @(negedge clk)
  53         begin
  54                 if (decode && rd)
  55                         odata <= switches;
  56                 else if (decode && wr)
  57                         ledout <= data;
  58         end
  59 endmodule
  60
  61 module CoreTop(
  62         input xtal,
  63         input [7:0] switches,
  64         output wire [7:0] leds,
  65         output serio,
  66         output wire [3:0] digits,
  67         output wire [7:0] seven);
  68
  69         wire clk;
  70         //IBUFG ibuf (.O(clk), .I(iclk));
  71
  72         CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
  73
  74         wire [15:0] addr;
  75         wire [7:0] data;
  76         wire wr, rd;
  77
  78         GBZ80Core core(
  79                 .clk(clk),
  80                 .busaddress(addr),
  81                 .busdata(data),
  82                 .buswr(wr),
  83                 .busrd(rd));
  84
  85         ROM rom(
  86                 .address(addr),
  87                 .data(data),
  88                 .clk(clk),
  89                 .wr(wr),
  90                 .rd(rd));
  91
  92         AddrMon amon(
  93     .addr(addr),
  94     .clk(clk),
  95     .digit(digits),
  96     .out(seven)
  97     );
  98
  99         Switches sw(
 100                 .address(addr),
 101                 .data(data),
 102                 .clk(clk),
 103                 .wr(wr),
 104                 .rd(rd),
 105                 .ledout(leds),
 106                 .switches(switches)
 107                 );
 108
 109         UART nouart (
 110     .clk(clk),
 111     .wr(wr),
 112     .rd(rd),
 113     .addr(addr),
 114     .data(data),
 115     .serial(serio)
 116     );
 117 endmodule
 118
 119 module TestBench();
 120         reg clk = 0;
 121         wire [15:0] addr;
 122         wire [7:0] data;
 123         wire wr, rd;
 124
 125 //      wire [7:0] leds;
 126 //      wire [7:0] switches;
 127
 128         always #10 clk <= ~clk;
 129         GBZ80Core core(
 130                 .clk(clk),
 131                 .busaddress(addr),
 132                 .busdata(data),
 133                 .buswr(wr),
 134                 .busrd(rd));
 135
 136         ROM rom(
 137                 .clk(clk),
 138                 .address(addr),
 139                 .data(data),
 140                 .wr(wr),
 141                 .rd(rd));
 142
 143 //      InternalRAM ram(
 144 //              .address(addr),
 145 //              .data(data),
 146 //              .clk(clk),
 147 //              .wr(wr),
 148 //              .rd(rd));
 149
 150         wire serio;
 151         UART uart(
 152                 .addr(addr),
 153                 .data(data),
 154                 .clk(clk),
 155                 .wr(wr),
 156                 .rd(rd),
 157                 .serial(serio));
 158
 159 //      Switches sw(
 160 //              .clk(clk),
 161 //              .address(addr),
 162 //              .data(data),
 163 //              .wr(wr),
 164 //              .rd(rd),
 165 //              .switches(switches),
 166 //              .leds(leds));
 167 endmodule