Spit lots of A out of the UART.

diff --git a/CPUDCM.xaw b/CPUDCM.xaw
index f28ae93df30c23638890364d7cb588faa9b9ebf1..28c77910208516985d488ac36208a2b7dbf9f7fd 100644 (file)
--- a/CPUDCM.xaw
+++ b/CPUDCM.xaw
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.4e
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.4e

-$92x6a=(`fgn#ga|htc,twimmj~x#k~ha.DSCDDhq&I[YIMB.yct5>6339$;8<5>8:35#mE709;0>;5=0/2347=5=81?86:!910815><0'934;>74:;-6l1<I[IC[DT>7:CQS_YHFESTOL]LAEKMCZEKC820M_YU_NLO]ZEKC@DTIUZJROCO50=FZ^PTCCBV_BNHMKYQIE_N=o5NRVX\KKJ^WMIFS^YFTBJJJBYDDB;;7L\XZ^MMH\YCL[UH<<>4ASUY[JHKQVNO^RM>109BVR\XGGFRSIJ]_BNH53=FZ^PTCCBV_EFQ[CJNXOFD\<;4ASUY[JHKQVLISHV[ESLBH44<I[]QSB@CY^KMWQYI]Do0M_YU_NLO]ZVJKM;>7L\XZ^MMH\YUMZO_SAAHIB3;?DTPRVEE@TQYAMKG[A@TWDEOIl5NSRM@[ROS@o1J[WQLLJ@VBQ_WM8;87LYU_BNH[JSSX\^TXT^Jc:CT^Z@KG^^R\H64AVX\TDTSl2K\VR]VNUJWKJJ33KE_D95MUGE7?FJL8?1H@F?7079@HN408<1H@F<W8:AOO7^609?0OAE6049@HNBQk2IGGIXPDHTJ@@3<KEAMN85LLJD[<>EKCOR:4=74CMIE\ZDRNo1H@FHW_CWECZOI[]i0OAEIX^FJRLBBm2IGGKVPMTNWMUJ^12IGGKVPOTV6?FJLAG;:7NBDIO]GMSOCMVHRS?l4CMIJJZOE]OM:<6MCKHL\MGSAOVCE_Yh4CMIJJZOE]OMTCXZ7;BNHMKYNFj1H@FGA_QGQMJBb3JF@ECQ\RB]W]UC6:2IGGB[[_QJBW@YT@@L_o6MCK^DFAADFKB30OBCBIUVF@2=DZLK_II84DBO\WUd<LJGT_]QFNRVg?ACTCL]TMIDZSU31?A@TWOXN]XKACX]NKAC6:2NG@RH]EPWFJF_XEFNN96J\SDL21>BR\PUHUNBJ_BMQV@ESAFD<7IQYAMWF<>C_\LXEMAo4F@AWKW_XBO?0JLB\E89EFZUH][IN56HFN^WMMQU?3OE^XR][R`9EKPRX]GC__l5IOTV\RDJRM;1MT<5F5:KAQCA692@BXYK]_HLSQQYSQYOh7GG[TDP\TN4WCj1AEYZJR^TBHPC13EEHGHJn;MM@O@BXG\^87AAX3:OK^2=JW_KGYH94NDVTKWM33GEEI<5@8:ME@ATDXLh0\EO\E^QKMCR>3YCEDL]MURc8TLHN[NDOII64PHLTMARO02ZYE@ZVPD33?UTHXVZBBD]NCUKUA0=W[JF@:6^\DNLF0>VTMG20\^GACEG@7>TT\k1XEJKWTDPMEI0<[@DL@Hm4SUCQPPVX_HC_:6][AUWP57=TQZ^NAR]VNBJQKKIR[:1_C]:4TSWF<>STMVH^JJ74URG\FP@@[<1]EHY>b:ZBSZPBZZCDB<j4XHNJJ]+_LK*;"<.\TT@#4+7'IZIBE>5WSU48\adXAm;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oy\7fdaa5:Y3>5[23R:1;P:4asuy7>bdek1}i\7f}foo"2*52<~angj6vl3r734`+2nn99<pNOp3g8DE~72O096<u\3d84f?1c2899:;m::01gf6}i?>0:7c97:59'33<0<2wX?i48b;5g>455>?i>6<:?cc9g3g<7280:w^=j:6`93a<6;;<=o84>3e`0?sR0:3:1=7?56zQ0a?1e2>n1=><96b7956be;2h=i7>50;192~"c2>i0(<k57d9'5c<0n2.9<79:;%50>f=e<90;6<=50;2x 34=;o1/i7<6;%d92d=#9809?6*>2;00?!742;>0(<:5229'50<2l2.::78n;%34>6=#910>n6*>9;6:?!7f2;;0(>m55c9'6d<23-9;6:5+308;?!532=30(>756:&0e?203-9i68l4$5392a=#<?087):=:458 15==>1/8849f:&7<?2<,=k19o5+4c86<>"3l3?37):j:c9'17<3k2.>5764$4g95>"1j3>27)9?:638 46=i2.:h7:i;%77>7=#=:027d=<:18'24<012.=?78i;:k1f?6=,?;1;45+6185b>"1;3<m76g98;29 37=?01/:=49f:9j23<72-<:6:74$7292c=<a?=1<7*91;5:?!072?l07d8;:18'24<012.=<78i;:k70?6=,?;1;45+6185b>=h::0;6)8>:6;8?j4?290/:<489:9l61<72-<:6:74;n06>5<#>80<565`2883>!062>307b<9:18'24<0121d>:4?:%42>2?<3f8h6=4+6084=>"1;3<m7)?l:308?j4c290/:<489:9l2f<72-<:6:o4$4d92c=<g<?1<7*91;5:?!042?l07b8::18'24<0121vn>850;094?6|,?819<5f5183>!062>30(;=56g98k0e=83.==796;%40>3`<3th9j7>52;294~"1:3897d;?:18'24<012.=?78i;:m6g?6=,?;1;45+6285b>=z{:?1<7<t=52976=:;?0>o6*>b;14?xu5m3:1>v3;0;0`?84a2<:0q~;9:182\7f8272<?0(;755b9~w6>=83;p1>85519'2<<282wx??4?:0y>6c<2k2.=57;l;|q03?6=8r.=57;l;|\7fm67<728qvb?=50;3xyk43290:wp`=5;295~{i:?0;6<urn3594?7|utwvLMMt2d8f=2160><vLMLt0|BCT~{GH
\ No newline at end of file
+$93x6a=(`fgn#ga|htc,twimmj~x#k~ha.DSCDDhq&I[YIMB.yct5>6339$;8<5>4:33*4><9?-cO=6?1:05?76)89:97?;>;5680+?7:2?;466!39:54=1<I[IC[DT>7:CQS_YHFESTOL]LAEKMCZEKC820M_YU_NLO]ZEKC@DTIUZJROCO50=FZ^PTCCBV_BNHMKYQIE_N=o5NRVX\KKJ^WMIFS^YFTBJJJBYDDB;;7L\XZ^MMH\YCL[UH<<>4ASUY[JHKQVNO^RM>109BVR\XGGFRSIJ]_BNH53=FZ^PTCCBV_EFQ[CJNXOFD\<;4ASUY[JHKQVLISHV[ESLBH44<I[]QSB@CY^KMWQYI]Do0M_YU_NLO]ZVJKM;>7L\XZ^MMH\YUMZO_SAAHIB3;?DTPRVEE@TQYAMKG[A@TWDEOIl5NSRM@[ROS@o1J[WQLLJ@VBQ_WM8;87LYU_BNH[JSSX\^TXT^Jc:CT^Z@KG^^R\H64AVX\TDTSl2K\VR]VNUJWKJJ33KE_D95MUGE7?FJL8?1H@F?7079@HN408<1H@F<W8:AOO7^609?0OAE6049@HNBQk2IGGIXPDHTJ@@3<KEAMN85LLJD[<>EKCOR:4=74CMIE\ZDRNo1H@FHW_CWECZOI[]i0OAEIX^FJRLBBm2IGGKVPMTNWMUJ^12IGGKVPOTV6?FJLAG;:7NBDIO]GMSOCMVHRS?l4CMIJJZOE]OM:<6MCKHL\MGSAOVCE_Yh4CMIJJZOE]OMTCXZ7;BNHMKYNFj1H@FGA_QGQMJBb3JF@ECQ\RB]W]UC6:2IGGB[[_QJBW@YT@@L_o6MCK^DFAADFKB30OBCBIUVF@2=DZLK_II84DBO\WUd<LJGT_]QFNRVg?ACTCL]TMIDZSU31?A@TWOXN]XKACX]NKAC6:2NG@RH]EPWFJF_XEFNN96J\SDL21>BR\PUHUNBJ_BMQV@ESAFD<7IQYAMWF<>C_\LXEMAo4F@AWKW_XBO?0JLB\E89EFZUH][IN56HFN^WMMQU?3OE^XR][R`9EKPRX]GC__l5IOTV\RDJRM;1MT<5F5:KAQCA692@BXYK]_HLSQQYSQYOh7GG[TDP\TN4WCj1AEYZJR^TBHPC13EEJHHJ9;MM@O@Bf3EEHGHJPOTV0?IIP;2GCV:5B_WCOQ@1<FL^\C_E;;OMMA4=H02EMHI\LPD`8TMGTMVYCEKZ6;QKMLDUE]Zk0\D@FSFLGAA><X@D\EIZG8:RQMHR^XL;;7]\@P^RJJLUFK]C]I85_SBNH2>VTLFDN86^\EO:8TVOIKMOH?6\\Tc9PMBC_\LXEMA84SHLDH@e<[]KYXX^PW@KW2>USI]_X=?5\YRVFIZU^FJBYCCAZS29WKU2<\[_N46[\E^@VBB?<]ZOTNXHHS49UM@Q6j2RJ[RXJRRKLJ4b<P@FBBU#WDC"3*4&T\\H+<#?/ARAJM6=_[]<0TilPIe33?]bjWDkac\7fXjrrklj46<PmgTAd``rWgqwlii=2Q;6=S:;Z293X2<i{}q?6jlmc9uawungg*:"=:4vifob>~d;z?;<h#:ff114xFGx::0LMv?:G87>4}T;l0<o79j:01123e2289on>ua7982?k1>2=1/;:485:\7fP7a<0k3=n6<==67a6>427kk1X9848c;5f>455>>;:659m7:Q0`?1d2>o1=><97039<2`73m=h6=4>:0yP7`<0k3=n6<==67a6>45cj:1}X:=50;395?0|[:o1;n48e;30630d=3;8ho=4b7d94?6=;3<p(i48d:&2a?1a3-;m65>4$32933=#?=0?7o:?:1827?6=8r.=?7=i;%g96<=#n3<i7)?>:318 44=::1/=>4=4:&20?443-;>68k4$0492g=#9>087)?7:4a8 4?=<01/=l4=1:&0g?3d3-8j6;5+318;?!56201/?94;9:&0=?1<,:k18:5+3c86g>"393<n7):9:29'07<202.??7;7;%66>26<,=2196*;a;7`?!2e2<30(9j5589'0`<d3-?969m4$4c9=>"2n3;0(;m5489'34<0:2.:<7l4$0f90c=#==097);<:`9j76<72-<96:o4$76935=<a;h1<7*92;5b?!062>:0(;:57198m3?=83.=>79n;%42>26<3`<<6=4+6384e>"193=;76g98;29 34=?h1/:<480:9j20<72-<96:o4$73935=<a=>1<7*92;5b?!062>:07b<<:18'27<0i21d>54?:%41>2g<3f8?6=4+6384e>=h:<0;6)8=:6c8?j4>290/:?48a:9l63<72-<96:o4;n04>5<#>;0<m65`2b83>!052>k0(;:5719'5f<5:21d>i4?:%41>2g<3f<o6=4+6384f>"183=;76a:6;29 34=?h1/:9480:9l23<72-<96:o4;|`02?6=:3:1<v*93;72?l37290/:?48a:&50?1732e>h7>5$7093d=#>=0<<65rb3d94?4=83:p(;=5239j15<72-<96:o4$76935=<g<n1<7*92;5b?!032>:07p}<5;296~;3839870=9:4f8 4d=;>1v\7f?k50;0x916=:j16>k4:0:\7fp12<728q68=4:6:&5e?3c3ty847>51z?02?373-<j68>4}r11>5<6s48m68j4$7c91a=z{:=1<7>t$7c91a=zug8?6=4>{|l11?6=9rwe>;4?:0y~j71=83;pqc<7:182\7fxh513:1=vsr}|BCG~572;ko8=ln2|BCF~6zHIZpqMN
\ No newline at end of file

diff --git a/FPGABoy.ise b/FPGABoy.ise
index c8729d3c44091249ec219e81ba61c4822fa6ef2b..5cb2ab77b4ffa9b6046d38c6afc61e1dde83dcd5 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index fc773779ceaae29f3206f94ff67aa8cd6d7e75be..3bc2b16f0e184c9a3e6ff8ea51d8cd82d97fa4b6 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -702,30 +702,31 @@ module InternalRAM(
        end
 endmodule
 
        end
 endmodule
 

-//module Switches(
-//     input [15:0] address,
-//     inout [7:0] data,
-//     input clk,
-//     input wr, rd,
-//     input [7:0] switches,
-//     output reg [7:0] ledout);
+module Switches(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd,
+       input [7:0] switches,
+       output reg [7:0] ledout);

        
        

-//     wire decode = address == 16'hFF51;
-//     reg [7:0] odata;
-//     wire idata = data;
-//     assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       wire decode = address == 16'hFF51;
+       reg [7:0] odata;
+       wire idata = data;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;

        
        

-//     always @(negedge clk)
-//     begin
-//             if (decode && rd)
-//                     odata <= switches;
-//             else if (decode && wr)
-//                     ledout <= data;
-//     end
-//endmodule
+       always @(negedge clk)
+       begin
+               if (decode && rd)
+                       odata <= switches;
+               else if (decode && wr)
+                       ledout <= data;
+       end
+endmodule

 
 module CoreTop(
 
 module CoreTop(

-       input iclk, xtal,
+       input xtal,
+       input [1:0] switches,

        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,


@@ -740,7 +741,9 @@ module CoreTop(
        wire [7:0] data;
        wire wr, rd;
        
        wire [7:0] data;
        wire wr, rd;
        

-       assign leds = iclk?{rd,wr,addr[5:0]}:data[7:0];
+       wire [7:0] ledout;
+       assign leds = switches[1] ? (switches[0]?{rd,wr,addr[5:0]}:data[7:0])
+                                               : ledout;

 
        GBZ80Core core(
                .clk(clk),
 
        GBZ80Core core(
                .clk(clk),


@@ -758,12 +761,29 @@ module CoreTop(
        
        AddrMon amon(
     .addr(addr), 
        
        AddrMon amon(
     .addr(addr), 

-    .clk(xtal), 
+    .clk(clk), 

     .digit(digits), 
     .out(seven)
     );
     .digit(digits), 
     .out(seven)
     );

-       
-       assign serio = 0;
+        
+       Switches sw(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .ledout(ledout),
+               .switches(0)
+               );
+
+       UART nouart (
+    .clk(clk), 
+    .wr(wr), 
+    .rd(rd), 
+    .addr(addr), 
+    .data(data), 
+    .serial(serio)
+    );

 endmodule
 
 module TestBench();
 endmodule
 
 module TestBench();

diff --git a/Uart.v b/Uart.v
index 1cc839a77ff584b615da50fc01676646897b4b14..f8ee27bc47997d4be5666903466cdedec6329fee 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -1,4 +1,4 @@
-`define IN_CLK 8400000
+`define IN_CLK 8388608

 `define OUT_CLK 9600
 `define CLK_DIV `IN_CLK / `OUT_CLK
 `define MMAP_ADDR 16'hFF50
 `define OUT_CLK 9600
 `define CLK_DIV `IN_CLK / `OUT_CLK
 `define MMAP_ADDR 16'hFF50


@@ -21,17 +21,16 @@ module UART(
 
        always @ (negedge clk)
        begin
 
        always @ (negedge clk)
        begin

-`define FUQING 4'b1010

                /* deal with diqing */
                if(new) begin
                /* deal with diqing */
                if(new) begin

-                       data_stor <= ~data;
+                       data_stor <= data;

                        have_data <= 1;
                        diqing <= 4'b0000;
                end else if (clkdiv == 0) begin
                        diqing <= diqing + 1;
                        if (have_data)
                                case (diqing)
                        have_data <= 1;
                        diqing <= 4'b0000;
                end else if (clkdiv == 0) begin
                        diqing <= diqing + 1;
                        if (have_data)
                                case (diqing)

-                               4'b0000: serial <= 1;
+                               4'b0000: serial <= 0;

                                4'b0001: serial <= data_stor[0];
                                4'b0010: serial <= data_stor[1];
                                4'b0011: serial <= data_stor[2];
                                4'b0001: serial <= data_stor[0];
                                4'b0010: serial <= data_stor[1];
                                4'b0011: serial <= data_stor[2];


@@ -40,7 +39,7 @@ module UART(
                                4'b0110: serial <= data_stor[5];
                                4'b0111: serial <= data_stor[6];
                                4'b1000: serial <= data_stor[7];
                                4'b0110: serial <= data_stor[5];
                                4'b0111: serial <= data_stor[6];
                                4'b1000: serial <= data_stor[7];

-                               4'b1001: serial <= 0;
+                               4'b1001: serial <= 1;

                                4'b1010: have_data <= 0;
                                default: $stop;
                        endcase
                                4'b1010: have_data <= 0;
                                default: $stop;
                        endcase

diff --git a/rom.hex b/rom.hex
index 79290c3208e2265ec6dbc713be736371aa5fe757..82a8f255f4601f4d13c578738b218d57fa057ff5 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -2,9 +2,9 @@
 05
 DF
 0E
 05
 DF
 0E

-51
+50

 3E
 3E

-40
+41

 E2
 C7
 00
 E2
 C7
 00