Spit lots of A out of the UART.
[fpgaboy.git] / Uart.v
CommitLineData
7d9d69c7 1`define IN_CLK 8388608
a0267255
JW
2`define OUT_CLK 9600
3`define CLK_DIV `IN_CLK / `OUT_CLK
4`define MMAP_ADDR 16'hFF50
5
6module UART(
7 input clk,
8 input wr,
9 input rd,
10 input [15:0] addr,
11 input [7:0] data,
12 output reg serial);
13
14 reg [7:0] data_stor = 0;
15 reg [15:0] clkdiv = 0;
16 reg have_data = 0;
17 reg data_end = 0;
18 reg [3:0] diqing = 4'b0000;
19
20 wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR);
21
22 always @ (negedge clk)
23 begin
a0267255
JW
24 /* deal with diqing */
25 if(new) begin
7d9d69c7 26 data_stor <= data;
a0267255
JW
27 have_data <= 1;
28 diqing <= 4'b0000;
29 end else if (clkdiv == 0) begin
30 diqing <= diqing + 1;
31 if (have_data)
32 case (diqing)
7d9d69c7 33 4'b0000: serial <= 0;
a0267255
JW
34 4'b0001: serial <= data_stor[0];
35 4'b0010: serial <= data_stor[1];
36 4'b0011: serial <= data_stor[2];
37 4'b0100: serial <= data_stor[3];
38 4'b0101: serial <= data_stor[4];
39 4'b0110: serial <= data_stor[5];
40 4'b0111: serial <= data_stor[6];
41 4'b1000: serial <= data_stor[7];
7d9d69c7 42 4'b1001: serial <= 1;
a0267255
JW
43 4'b1010: have_data <= 0;
44 default: $stop;
45 endcase
46 end
47
48 /* deal with clkdiv */
49 if((new && !have_data) || clkdiv == `CLK_DIV)
50 clkdiv <= 0;
51 else
52 clkdiv <= clkdiv + 1;
53 end
54endmodule
This page took 0.022382 seconds and 4 git commands to generate.