JR and JRCC

diff --git a/FPGABoy.ise b/FPGABoy.ise
index d8f72a2f146dcace36e5e5d0c488158b41379039..cf8e69757eb987a5c3ebe3abcf10e59e3e11d6a1 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 0697295dec07e734c6c2602fd403e00fccc3944a..77c3649372a715fc6b5445302332ed3232c66143 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -42,6 +42,8 @@
 `define INSN_JPCC_imm          8'b110xx010
 `define INSN_ALU_A             8'b00xxx111
 `define INSN_JP_HL                     8'b11101001
 `define INSN_JPCC_imm          8'b110xx010
 `define INSN_ALU_A             8'b00xxx111
 `define INSN_JP_HL                     8'b11101001

+`define INSN_JR_imm                    8'b00011000
+`define INSN_JRCC_imm          8'b001xx000

 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01
 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01


@@ -485,6 +487,30 @@ module GBZ80Core(
                        `INSN_JP_HL: begin
                                `EXEC_NEWCYCLE;
                        end
                        `INSN_JP_HL: begin
                                `EXEC_NEWCYCLE;
                        end

+                       `INSN_JR_imm,`INSN_JRCC_imm: begin
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;
+                                       end
+                               1: begin
+                                               `EXEC_INC_PC;
+                                               if (opcode[5]) begin    // i.e., JP cc,nn
+                                                       /* We need to check the condition code to bail out. */
+                                                       case (opcode[4:3])
+                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       endcase
+                                               end
+                                       end
+                               2:      begin
+                                               `EXEC_NEWCYCLE;
+                                       end
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -792,6 +818,15 @@ module GBZ80Core(
                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                        {registers[`REG_H],registers[`REG_L]};
                        end
                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                        {registers[`REG_H],registers[`REG_L]};
                        end

+                       `INSN_JR_imm,`INSN_JRCC_imm: begin
+                               case (cycle)
+                               0:      begin /* type F */ end
+                               1:      tmp <= rdata;
+                               2: {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                               {registers[`REG_PCH],registers[`REG_PCL]} +
+                                               {tmp[7]?8'hFF:8'h00,tmp};
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase

diff --git a/rom.asm b/rom.asm
index 02f095b50e00470b469615b586435f55b34de341..c2b759883eac10bbd2b231f217cc8df3ecafdce6 100644 (file)
--- a/rom.asm
+++ b/rom.asm
@@ -150,6 +150,24 @@ insntest:
        ld hl, .xorhlfail
        jp nz, .fail
        
        ld hl, .xorhlfail
        jp nz, .fail
        

+       ; Test JP (HL)
+       ld hl, .jphl
+       jp [hl]
+       ld hl, .jphlfail
+       jp .fail
+       rst $00
+.jphl:
+
+       ; Test JR
+       ld a, $FF
+       ld b, $00
+       cp b
+       jr nz,.jr
+       ld hl, .jrfail
+       jp .fail
+       rst $00
+.jr:
+       

        ; Test CP.
        ld hl, .cpfail
        ld a, $10
        ; Test CP.
        ld hl, .cpfail
        ld a, $10


@@ -183,6 +201,10 @@ insntest:
        db $FF
 .xorhlfail:
        db "XOR [HL] test failed.",$0D,$0A,0
        db $FF
 .xorhlfail:
        db "XOR [HL] test failed.",$0D,$0A,0

+.jphlfail:
+       db "JP [HL] test failed.",$0D,$0A,0
+.jrfail:
+       db "JR test failed.",$0D,$0A,0

 .cpfail:
        db "CP test failed.",$0D,$0A,0
 .cplfail:
 .cpfail:
        db "CP test failed.",$0D,$0A,0
 .cplfail: