Move alu_ext to its own file

diff --git a/broken-tests b/broken-tests
index e388d35cf125bf8d74b7ff44b39f021ebdfbcd17..bae68c98d34e05d1f4036a7d4e28ce2cc20fa468 100644 (file)
--- a/broken-tests
+++ b/broken-tests
@@ -37,5 +37,4 @@ TEST 10: SP/HL instructions
 E8 01 (ADD SP, 1)
 E8 FF (ADD SP, -1)
 F8 01 (LD HL, SP+1)
-F8 FF (LD HL, SP-1)
-
+F8 FF (LD HL, SP-1)
\ No newline at end of file

diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index a79b78a28946c329661f11fcf84e08b97eabb7a0..b5a502cefeef17761325ff3066699b1eef174214 100644 (file)
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -150,65 +150,6 @@ module GBZ80Core(
 `include "allinsns.v"
 `undef LOCALWIRES
 
-       wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
-       wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
-       wire [7:0] alu_res;
-       wire [3:0] f_res;
-
-       assign rlc   = {tmp[6:0],tmp[7]};
-       assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
-                       ,2'b0,
-                       tmp[7]};
-
-       assign rrc   = {tmp[0],tmp[7:1]};
-       assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[0]};
-
-       assign rl    = {tmp[6:0],`_F[4]};
-       assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[7]};
-
-       assign rr    = {`_F[4],tmp[7:1]};
-       assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[0]};
-
-       assign sla   = {tmp[6:0],1'b0};
-       assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[7]};
-
-       assign sra   = {tmp[7],tmp[7:1]};
-//     assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
-
-       assign swap  = {tmp[3:0],tmp[7:4]};
-       assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
-                       3'b0};
-
-       assign srl   = {1'b0,tmp[7:1]};
-       assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
-                       2'b0,
-                       tmp[0]};
-       assign sraf  = srlf;
-
-       /*  Y U Q  */
-       assign {alu_res,f_res} =
-               opcode[5] ? (
-                       opcode[4] ? (
-                               opcode[3] ? {srl,srlf} : {swap,swapf}
-                       ) : (
-                               opcode[3] ? {sra,sraf} : {sla,slaf}
-                       )
-               ) : (
-                       opcode[4] ? (
-                               opcode[3] ? {rr,rrf} : {rl,rlf}
-                       ) : (
-                               opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
-                       )
-               );
-
        initial begin
                `_A <= 0;
                `_B <= 0;

diff --git a/core/insn_alu_ext.v b/core/insn_alu_ext.v
index b4046e80c48316bf7179c0a0aea9b6227f91068f..19855868054e8a02f02318bbcb2a2de056dd1802 100644 (file)
--- a/core/insn_alu_ext.v
+++ b/core/insn_alu_ext.v
@@ -1,5 +1,66 @@
 `define INSN_ALU_EXT           9'b100xxxxxx
 
+`ifdef LOCALWIRES
+       wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
+       wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
+       wire [7:0] alu_res;
+       wire [3:0] f_res;
+
+       assign rlc   = {tmp[6:0],tmp[7]};
+       assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
+                       ,2'b0,
+                       tmp[7]};
+
+       assign rrc   = {tmp[0],tmp[7:1]};
+       assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[0]};
+
+       assign rl    = {tmp[6:0],`_F[4]};
+       assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[7]};
+
+       assign rr    = {`_F[4],tmp[7:1]};
+       assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[0]};
+
+       assign sla   = {tmp[6:0],1'b0};
+       assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[7]};
+
+       assign sra   = {tmp[7],tmp[7:1]};
+//     assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
+
+       assign swap  = {tmp[3:0],tmp[7:4]};
+       assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
+                       3'b0};
+
+       assign srl   = {1'b0,tmp[7:1]};
+       assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
+                       2'b0,
+                       tmp[0]};
+       assign sraf  = srlf;
+
+       /*  Y U Q  */
+       assign {alu_res,f_res} =
+               opcode[5] ? (
+                       opcode[4] ? (
+                               opcode[3] ? {srl,srlf} : {swap,swapf}
+                       ) : (
+                               opcode[3] ? {sra,sraf} : {sla,slaf}
+                       )
+               ) : (
+                       opcode[4] ? (
+                               opcode[3] ? {rr,rrf} : {rl,rlf}
+                       ) : (
+                               opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
+                       )
+               );
+`endif
+
 `ifdef EXECUTE
        `INSN_ALU_EXT: begin
                if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))