Move alu_ext to its own file
[fpgaboy.git] / core / insn_alu_ext.v
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1`define INSN_ALU_EXT 9'b100xxxxxx
2
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3`ifdef LOCALWIRES
4 wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
5 wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
6 wire [7:0] alu_res;
7 wire [3:0] f_res;
8
9 assign rlc = {tmp[6:0],tmp[7]};
10 assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0)
11 ,2'b0,
12 tmp[7]};
13
14 assign rrc = {tmp[0],tmp[7:1]};
15 assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0),
16 2'b0,
17 tmp[0]};
18
19 assign rl = {tmp[6:0],`_F[4]};
20 assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
21 2'b0,
22 tmp[7]};
23
24 assign rr = {`_F[4],tmp[7:1]};
25 assign rrf = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
26 2'b0,
27 tmp[0]};
28
29 assign sla = {tmp[6:0],1'b0};
30 assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
31 2'b0,
32 tmp[7]};
33
34 assign sra = {tmp[7],tmp[7:1]};
35// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf =
36
37 assign swap = {tmp[3:0],tmp[7:4]};
38 assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
39 3'b0};
40
41 assign srl = {1'b0,tmp[7:1]};
42 assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
43 2'b0,
44 tmp[0]};
45 assign sraf = srlf;
46
47 /* Y U Q */
48 assign {alu_res,f_res} =
49 opcode[5] ? (
50 opcode[4] ? (
51 opcode[3] ? {srl,srlf} : {swap,swapf}
52 ) : (
53 opcode[3] ? {sra,sraf} : {sla,slaf}
54 )
55 ) : (
56 opcode[4] ? (
57 opcode[3] ? {rr,rrf} : {rl,rlf}
58 ) : (
59 opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
60 )
61 );
62`endif
63
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64`ifdef EXECUTE
65 `INSN_ALU_EXT: begin
66 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
67 `EXEC_READ(`_HL)
68 else begin
69 `EXEC_INC_PC
70 case (opcode[2:0])
71 `INSN_reg_A: tmp <= `_A;
72 `INSN_reg_B: tmp <= `_B;
73 `INSN_reg_C: tmp <= `_C;
74 `INSN_reg_D: tmp <= `_D;
75 `INSN_reg_E: tmp <= `_E;
76 `INSN_reg_H: tmp <= `_H;
77 `INSN_reg_L: tmp <= `_L;
78 `INSN_reg_dHL: tmp <= rdata;
79 endcase
80 end
81 end
82`endif
83
84`ifdef WRITEBACK
85 `INSN_ALU_EXT: begin
86 if (opcode[2:0] == `INSN_reg_dHL) begin
87 if(cycle == 0) begin end
88 else if(cycle == 1) begin
89 `EXEC_WRITE(`_HL, alu_res)
e7fe9dc2 90 `_F <= {f_res,`_F[3:0]};
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91 end else begin
92 `EXEC_NEWCYCLE
93 end
94 end else begin
95 case(opcode[2:0])
96 `INSN_reg_B: `_B <= alu_res;
97 `INSN_reg_C: `_C <= alu_res;
98 `INSN_reg_D: `_D <= alu_res;
99 `INSN_reg_E: `_E <= alu_res;
100 `INSN_reg_H: `_H <= alu_res;
101 `INSN_reg_L: `_L <= alu_res;
102 `INSN_reg_A: `_A <= alu_res;
103 `INSN_reg_dHL: begin end /* eat dicks */
104 endcase
105 `_F <= {f_res,`_F[3:0]};
106 `EXEC_NEWCYCLE
107 end
108 end
109`endif
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