]>
Joshua Wise's Git repositories - fpgaboy.git/commitdiff
summary |
shortlog |
log |
commit | commitdiff |
tree
raw |
patch | inline |
side by side (from parent 1:
a00483d )
// .wr(wr),
// .rd(rd));
-// wire serio;
-// UART uart(
-// .addr(addr),
-// .data(data),
-// .clk(clk),
-// .wr(wr),
-// .rd(rd),
-// .serial(serio));
+ wire serio;
+ UART uart(
+ .addr(addr),
+ .data(data),
+ .clk(clk),
+ .wr(wr),
+ .rd(rd),
+ .serial(serio));
// Switches sw(
// .clk(clk),
-ca
-08
-00
-00
-00
-00
-00
-00
+0e
+50
+06
+00
+f2
+b8
+c2
+04
+00
+3e
+41
+e2
+f2
+b8
+c2
+0c
+00
+3e
+42
+e2
c3
00
00
00
00
00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
This page took 0.026875 seconds and 4 git commands to generate.