Poke the UART with a stick. ABABABABABABAB

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 8dfc411d2ba4f50bddbb6b7e25b3fcb106f10b22..c429431d73867de7fbd4250bc3eaddf3a56a582b 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/System.v b/System.v
index 53e6257f601762ceb5ecd2e27de03eed8c0c029b..259656abe330f3d4040723c7ed544401573c6c94 100644 (file)
--- a/System.v
+++ b/System.v
@@ -147,14 +147,14 @@ module TestBench();
 //             .wr(wr),
 //             .rd(rd));
 
 //             .wr(wr),
 //             .rd(rd));
 

-//     wire serio;
-//     UART uart(
-//             .addr(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd),
-//             .serial(serio));
+       wire serio;
+       UART uart(
+               .addr(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .serial(serio));

        
 //     Switches sw(
 //             .clk(clk),
        
 //     Switches sw(
 //             .clk(clk),

diff --git a/rom.hex b/rom.hex
index 977ed30a6fbc0b27318fee9864470daf1a917b5d..504108d73fb2eac97236dadd745ccdb4e6ce6748 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -1,11 +1,23 @@
-ca
-08
-00
-00
-00
-00
-00 
-00
+0e
+50
+06
+00
+f2
+b8
+c2
+04
+00
+3e
+41
+e2
+f2
+b8
+c2
+0c
+00
+3e
+42
+e2

 c3
 00
 00
 c3
 00
 00


@@ -2034,15 +2046,3 @@ c3
 00
 00
 00
 00
 00
 00

-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00