First attempt at fixing DAA. Add ld (nn), sp.

diff --git a/Makefile b/Makefile
index 732727ccd9eecb4ec081a0298591a3dce89e6da4..eaf0a6e80081dc714f8e9184ed46bdb45291b92c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -12,7 +12,7 @@ VLOGS_ALL = $(VLOGS) core/insn_call-callcc.v core/insn_incdec16.v \
        core/insn_vop_intr.v core/insn_ldm8_a.v core/insn_ldm16_a.v \
        core/insn_ldbcde_a.v core/insn_alu_ext.v core/insn_bit.v \
        core/insn_two_byte.v core/insn_incdec_reg8.v core/insn_add_hl.v \
-       core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v
+       core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v core/insn_ld_nn_sp.v
 
 all: CoreTop.svf
 

diff --git a/core/GBZ80Core.v b/core/GBZ80Core.v
index fcc3337e13b2244aa4d423fae5a3c3faa81c21e0..a79b78a28946c329661f11fcf84e08b97eabb7a0 100644 (file)
--- a/core/GBZ80Core.v
+++ b/core/GBZ80Core.v
@@ -146,6 +146,10 @@ module GBZ80Core(
 
        reg ie, iedelay;
 
+`define LOCALWIRES
+`include "allinsns.v"
+`undef LOCALWIRES
+
        wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
        wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
        wire [7:0] alu_res;

diff --git a/core/allinsns.v b/core/allinsns.v
index 4ecd2b1a110d4ae3065d1ca8967472c52c1404bf..b7065ef04e42a19849f6ac57466205f87d049420 100644 (file)
--- a/core/allinsns.v
+++ b/core/allinsns.v
@@ -32,3 +32,4 @@
 `include "insn_add_hl.v"
 `include "insn_ldhl_sp_imm8.v"
 `include "insn_add_sp_imm8.v"
+`include "insn_ld_nn_sp.v"
\ No newline at end of file

diff --git a/core/insn_alu_a.v b/core/insn_alu_a.v
index 580643884bf36fcda66d94d1e28e0dfa030b6d06..a51f8bb0adb2c84fd895768748b973d4c8b7e7b9 100644 (file)
--- a/core/insn_alu_a.v
+++ b/core/insn_alu_a.v
@@ -9,6 +9,18 @@
 
 `define INSN_ALU_A             9'b000xxx111
 
+`ifdef LOCALWIRES
+       /* Y U Q */
+       /* Derived from MESS opc_main.h */
+       wire [8:0] daa_tmp_n0_h = ((`_F & `FLAG_H) || (`_A[3:0] > 9)) ? {1'b0,`_A} + 9'h06 : {1'b0,`_A};
+       wire [8:0] daa_tmp_n0 = ((`_F & `FLAG_C) || (daa_tmp_n0_h[8:4] > 9)) ? daa_tmp_n0_h + 9'h60 : daa_tmp_n0_h;
+       
+       wire [8:0] daa_tmp_n_h1 = (`_F & `FLAG_H) ? ({1'b0,`_A} - 9'h06) : {1'b0,`_A};
+       wire [8:0] daa_tmp_n_h2 = ((`_F & `FLAG_H) && !(`_F & `FLAG_C)) ? {1'b0,daa_tmp_n_h1[7:0]} : daa_tmp_n_h1;
+       wire [8:0] daa_tmp_n = (`_F & `FLAG_C) ? (daa_tmp_n_h2 - 9'h60) : daa_tmp_n_h2;
+       wire [8:0] daa_tmp = (`_F & `FLAG_N) ? daa_tmp_n : daa_tmp_n0;
+`endif
+
 `ifdef EXECUTE
        `INSN_ALU_A: begin
                `EXEC_NEWCYCLE
@@ -36,76 +48,13 @@
                        `_F <= {`_F[7:5],`_A[0],`_F[3:0]};
                end
                `INSN_alu_DAA: begin
-                       if (`_F[6]) begin                               
-                               if (`_F[4]) begin
-                                       if(`_A[3:0] >= 4'h6 && `_A[7:4] >= 4'h6 && `_F[5]) begin
-                                               `_A <= `_A + 8'h9A;
-                                               `_F <= {((`_A + 8'h9A) == 8'b0), `_F[6:0]};
-                                       end
-                                       else begin
-                                               `_A <= `_A + 8'hA0;
-                                               `_F <= {((`_A + 8'hA0) == 8'b0), `_F[6:0]};
-                                       end
-                               end
-                               else begin
-                                       if(`_A[3:0] <= 4'h9 && `_A[7:4] <= 4'h9 && !`_F[5]) begin
-                                               `_F <= {(`_A == 8'b0), `_F[6:0]};
-                                       end
-                                       else begin
-                                               `_A <= `_A + 8'hFA;
-                                               `_F <= {((`_A + 8'hFA) == 8'b0), `_F[6:0]};
-                                       end
-                               end
-                       end
-                       else begin
-                               if (`_F[4]) begin
-                                       if(`_F[5]) begin
-                                               `_A <= `_A + 8'h66;
-                                               `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]};
-                                       end
-                                       else if (`_A[3:0] > 4'h9) begin
-                                               `_A <= `_A + 8'h66;
-                                               `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:0]};
-                                       end
-                                       else begin
-                                               `_A <= `_A + 8'h60;
-                                               `_F <= {((`_A + 8'h60) == 8'b0), `_F[6:0]};
-                                       end
-                               end
-                               else begin
-                                       if(`_F[5]) begin
-                                               if(`_A[7:4] > 4'h9) begin
-                                                       `_A <= `_A + 8'h66;
-                                                       `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]};
-                                               end
-                                               else begin
-                                                       `_A <= `_A + 8'h06;
-                                                       `_F <= {((`_A + 8'h06) == 8'b0), `_F[6:0]};
-                                               end
-                                       end
-                                       else begin
-                                               if(`_A[3:0] > 4'h9) begin
-                                                       if (`_A[7:4] > 4'h8) begin
-                                                               `_A <= `_A + 8'h66;
-                                                               `_F <= {((`_A + 8'h66) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]};
-                                                       end
-                                                       else begin
-                                                               `_A <= `_A + 8'h06;
-                                                               `_F <= {((`_A + 8'h06) == 8'b0), `_F[6:0]};
-                                                       end
-                                               end
-                                               else begin
-                                                       if (`_A[7:4] > 4'h9) begin
-                                                               `_A <= `_A + 8'h60;
-                                                               `_F <= {((`_A + 8'h60) == 8'b0), `_F[6:5], 1'b1, `_F[3:0]};
-                                                       end
-                                                       else begin
-                                                               `_F <= {(`_A == 8'b0), `_F[6:0]};
-                                                       end
-                                               end
-                                       end
-                               end
-                       end
+                       `_A <= daa_tmp[7:0];
+                       `_F <= {
+                                       (daa_tmp[7:0] == 0) ? 1'b1 : 8'b0, /* Z */
+                                       2'b00, /* NH */
+                                       daa_tmp[8], /* C */
+                                       `_F[3:0]
+                               };
                end
                `INSN_alu_CPL: begin
                        `_A <= ~`_A;

diff --git a/core/insn_ld_nn_sp.v b/core/insn_ld_nn_sp.v
new file mode 100644 (file)
index 0000000..ade83fe
--- /dev/null
+++ b/core/insn_ld_nn_sp.v
@@ -0,0 +1,39 @@
+`define INSN_LD_NN_SP          9'b000001000
+
+`ifdef EXECUTE
+       `INSN_LD_NN_SP: begin
+               case (cycle)
+               0:      begin
+                               `EXEC_INC_PC
+                               `EXEC_READ(`_PC + 16'h0001)
+                       end
+               1:      begin
+                               `EXEC_INC_PC
+                               `EXEC_READ(`_PC + 16'h0001)
+                       end
+               2:      begin
+                               `EXEC_WRITE(({tmp, rdata}), `_SPL)
+                       end
+               3:      begin
+                               `EXEC_WRITE(({tmp, tmp2}), `_SPH)
+                       end
+               4:      begin
+                               `EXEC_NEWCYCLE
+                               `EXEC_INC_PC
+                       end
+               endcase
+       end
+`endif
+
+`ifdef WRITEBACK
+       `INSN_LD_NN_SP: begin
+               case (cycle)
+               0:      begin end
+               1:      tmp <= rdata;
+               2:      {tmp, tmp2} <= {tmp, rdata} + 1;
+               3:      begin end
+               4:      begin end
+               endcase
+       end
+`endif
+