fcc3337e13b2244aa4d423fae5a3c3faa81c21e0
[fpgaboy.git] / core / GBZ80Core.v
1 `define REG_A   0
2 `define REG_B   1
3 `define REG_C   2
4 `define REG_D   3
5 `define REG_E   4
6 `define REG_F   5
7 `define REG_H   6
8 `define REG_L   7
9 `define REG_SPH 8
10 `define REG_SPL 9
11 `define REG_PCH 10
12 `define REG_PCL 11
13
14 `define _A      registers[`REG_A]
15 `define _B      registers[`REG_B]
16 `define _C      registers[`REG_C]
17 `define _D      registers[`REG_D]
18 `define _E      registers[`REG_E]
19 `define _F      registers[`REG_F]
20 `define _H      registers[`REG_H]
21 `define _L      registers[`REG_L]
22 `define _SPH    registers[`REG_SPH]
23 `define _SPL    registers[`REG_SPL]
24 `define _PCH    registers[`REG_PCH]
25 `define _PCL    registers[`REG_PCL]
26 `define _AF     {`_A, `_F}
27 `define _BC     {`_B, `_C}
28 `define _DE     {`_D, `_E}
29 `define _HL     {`_H, `_L}
30 `define _SP     {`_SPH, `_SPL}
31 `define _PC     {`_PCH, `_PCL}
32
33 `define FLAG_Z  8'b10000000
34 `define FLAG_N  8'b01000000
35 `define FLAG_H  8'b00100000
36 `define FLAG_C  8'b00010000
37
38 `define STATE_FETCH             2'h0
39 `define STATE_DECODE            2'h1
40 `define STATE_EXECUTE           2'h2
41 `define STATE_WRITEBACK         2'h3
42
43 `define INSN_VOP_INTR           9'b011111100    // 0xFC is grabbed by the fetch if there is an interrupt pending.
44 `define INSN_RES                9'b110xxxxxx
45 `define INSN_SET                9'b111xxxxxx
46
47 `define INSN_cc_NZ              2'b00
48 `define INSN_cc_Z               2'b01
49 `define INSN_cc_NC              2'b10
50 `define INSN_cc_C               2'b11
51
52 `define INSN_reg_A              3'b111
53 `define INSN_reg_B              3'b000
54 `define INSN_reg_C              3'b001
55 `define INSN_reg_D              3'b010
56 `define INSN_reg_E              3'b011
57 `define INSN_reg_H              3'b100
58 `define INSN_reg_L              3'b101
59 `define INSN_reg_dHL            3'b110
60 `define INSN_reg16_BC           2'b00
61 `define INSN_reg16_DE           2'b01
62 `define INSN_reg16_HL           2'b10
63 `define INSN_reg16_SP           2'b11
64 `define INSN_stack_AF           2'b11
65 `define INSN_stack_BC           2'b00
66 `define INSN_stack_DE           2'b01
67 `define INSN_stack_HL           2'b10
68 `define INSN_alu_ADD            3'b000
69 `define INSN_alu_ADC            3'b001
70 `define INSN_alu_SUB            3'b010
71 `define INSN_alu_SBC            3'b011
72 `define INSN_alu_AND            3'b100
73 `define INSN_alu_XOR            3'b101
74 `define INSN_alu_OR             3'b110
75 `define INSN_alu_CP             3'b111          // Oh lawd, is dat some CP?
76 `define INSN_alu_RLC            3'b000
77 `define INSN_alu_RRC            3'b001
78 `define INSN_alu_RL             3'b010
79 `define INSN_alu_RR             3'b011
80 `define INSN_alu_DA_SLA         3'b100
81 `define INSN_alu_CPL_SRA        3'b101
82 `define INSN_alu_SCF_SWAP       3'b110
83 `define INSN_alu_CCF_SRL        3'b111
84
85 `define EXEC_INC_PC             `_PC <= `_PC + 1;
86 `define EXEC_NEXTADDR_PCINC     address <= `_PC + 1;
87 `define EXEC_NEWCYCLE           begin newcycle <= 1; rd <= 1; wr <= 0; end
88 `define EXEC_NEWCYCLE_TWOBYTE   begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
89 `ifdef isim
90         `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
91         `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
92 `else
93         /* Work around XST's retarded bugs :\ */
94         `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
95         `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
96 `endif
97
98 module GBZ80Core(
99         input clk,
100         inout [15:0] bus0address,       /* BUS_* is latched on STATE_FETCH. */
101         inout [7:0] bus0data,
102         inout bus0wr, bus0rd,
103         inout [15:0] bus1address,       /* BUS_* is latched on STATE_FETCH. */
104         inout [7:0] bus1data,
105         inout bus1wr, bus1rd,
106         input irq, output reg irqack, input [7:0] jaddr,
107         output reg [1:0] state);
108
109 //      reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
110         reg [2:0] cycle;                                        /* Cycle for instructions. */
111         
112         reg [7:0] registers[11:0];
113         
114         reg [15:0] address;                             /* Address for the next bus operation. */
115         
116         reg [8:0] opcode;                               /* Opcode from the current machine cycle. */
117
118         reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
119         reg rd, wr, newcycle, twobyte;
120         
121         reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
122         
123         reg [7:0] buswdata;
124         wire [7:0] busdata;
125         
126         reg [15:0] busaddress;
127         reg buswr, busrd;
128         
129         reg bootstrap_enb;
130         
131         wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF))   /* 0 or 1 depending on which bus */
132                 `ifdef isim
133                         || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
134                 `endif
135                         ;
136                 
137         assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
138         assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
139         assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
140         assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
141         assign busdata = (bus == 0) ? bus0data : bus1data;
142         assign bus0rd = (bus == 0) ? busrd : 1'b0;
143         assign bus1rd = (bus == 1) ? busrd : 1'b0;
144         assign bus0wr = (bus == 0) ? buswr : 1'b0;
145         assign bus1wr = (bus == 1) ? buswr : 1'b0;
146
147         reg ie, iedelay;
148
149         wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
150         wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
151         wire [7:0] alu_res;
152         wire [3:0] f_res;
153
154         assign rlc   = {tmp[6:0],tmp[7]};
155         assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
156                         ,2'b0,
157                         tmp[7]};
158
159         assign rrc   = {tmp[0],tmp[7:1]};
160         assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
161                         2'b0,
162                         tmp[0]};
163
164         assign rl    = {tmp[6:0],`_F[4]};
165         assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
166                         2'b0,
167                         tmp[7]};
168
169         assign rr    = {`_F[4],tmp[7:1]};
170         assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
171                         2'b0,
172                         tmp[0]};
173
174         assign sla   = {tmp[6:0],1'b0};
175         assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
176                         2'b0,
177                         tmp[7]};
178
179         assign sra   = {tmp[7],tmp[7:1]};
180 //      assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
181
182         assign swap  = {tmp[3:0],tmp[7:4]};
183         assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
184                         3'b0};
185
186         assign srl   = {1'b0,tmp[7:1]};
187         assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
188                         2'b0,
189                         tmp[0]};
190         assign sraf  = srlf;
191
192         /*  Y U Q  */
193         assign {alu_res,f_res} =
194                 opcode[5] ? (
195                         opcode[4] ? (
196                                 opcode[3] ? {srl,srlf} : {swap,swapf}
197                         ) : (
198                                 opcode[3] ? {sra,sraf} : {sla,slaf}
199                         )
200                 ) : (
201                         opcode[4] ? (
202                                 opcode[3] ? {rr,rrf} : {rl,rlf}
203                         ) : (
204                                 opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
205                         )
206                 );
207
208         initial begin
209                 `_A <= 0;
210                 `_B <= 0;
211                 `_C <= 0;
212                 `_D <= 0;
213                 `_E <= 0;
214                 `_F <= 0;
215                 `_H <= 0;
216                 `_L <= 0;
217                 `_PCH <= 0;
218                 `_PCL <= 0;
219                 `_SPH <= 0;
220                 `_SPL <= 0;
221                 rd <= 1;
222                 wr <= 0;
223                 newcycle <= 1;
224                 state <= 0;
225                 cycle <= 0;
226                 busrd <= 0;
227                 buswr <= 0;
228                 busaddress <= 0;
229                 ie <= 0;
230                 iedelay <= 0;
231                 opcode <= 0;
232                 state <= `STATE_WRITEBACK;
233                 cycle <= 0;
234                 twobyte <= 0;
235                 bootstrap_enb <= 1;
236                 irqack <= 0;
237         end
238
239         always @(negedge clk)   /* Set things up at the negedge to prepare for the posedge. */
240                 case (state)
241                 `STATE_FETCH: begin
242                         if (newcycle) begin
243                                 busaddress <= `_PC;
244                                 buswr <= 0;
245                                 busrd <= 1;
246                         end else begin
247                                 busaddress <= address;
248                                 buswr <= wr;
249                                 busrd <= rd;
250                                 if (wr) begin
251                                         buswdata <= wdata;
252                                         if (address == 16'hFF50)
253                                                 bootstrap_enb <= 0;
254                                 end
255                         end
256                 end
257                 `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
258                         buswr <= 0;
259                         busrd <= 0;
260                 end
261                 endcase
262         
263         always @(posedge clk)
264                 case (state)
265                 `STATE_FETCH: begin
266                         /* Things are set up in negedge so that something looking on posedge will get his shit. */
267                         state <= `STATE_DECODE;
268                 end
269                 `STATE_DECODE: begin
270                         if (newcycle) begin
271                                 if (twobyte) begin
272                                         opcode <= {1'b1,busdata};
273                                         twobyte <= 0;
274                                 end else if (ie && irq)
275                                         opcode <= `INSN_VOP_INTR;
276                                 else
277                                         opcode <= {1'b0,busdata};
278                                 newcycle <= 0;
279                                 rdata <= busdata;
280                                 cycle <= 0;
281                         end else begin
282                                 if (rd) rdata <= busdata;       /* Still valid because peripherals are now expected to keep it held valid. */
283                                 cycle <= cycle + 1;
284                         end
285                         if (iedelay) begin
286                                 ie <= 1;
287                                 iedelay <= 0;
288                         end
289                         wr <= 0;
290                         rd <= 0;
291                         address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
292                         wdata <= 8'bxxxxxxxx;
293                         state <= `STATE_EXECUTE;
294                 end
295                 `STATE_EXECUTE: begin
296                 `ifdef isim
297                         if (opcode[7:0] === 8'bxxxxxxxx)
298                                 $stop;
299                 `endif
300                         casex (opcode)
301                         `define EXECUTE
302                         `include "allinsns.v"
303                         `undef EXECUTE
304                         default:
305                                 $stop;
306                         endcase
307                         state <= `STATE_WRITEBACK;
308                 end
309                 `STATE_WRITEBACK: begin
310                         casex (opcode)
311                         `define WRITEBACK
312                         `include "allinsns.v"
313                         `undef WRITEBACK
314                         default:
315                                 $stop;
316                         endcase
317                         state <= `STATE_FETCH;
318                 end
319                 endcase
320 endmodule
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