ld sp, $DFF0
+ ld c, $07
+ ld a, $04 ;start timer, 4.096KHz
+ ld [c], a
+
+ ld hl, $DF81
+ xor a
+ ld [hl], a
+
ld hl, signon
call puts
+
+ ei
call memtest
call insntest
call waitsw
+
+ di
jr main
signon:
db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
+ section "fuq",HOME[$100]
+irqhand:
+ PUSH AF
+ PUSH BC
+ PUSH DE
+ PUSH HL
+
+ xor a
+ ld c, $0F ; ack the irq
+ ld [c], a
+
+ ld a, $41 ; print A
+ call putc
+
+ ld hl, $DF81
+ ld a, [hl]
+ ld b, 1
+ add b
+ ld c, $51
+ ld [c], a
+ ld [hl], a
+
+
+ POP HL
+ POP DE
+ POP BC
+ POP AF
+ RETI
+ db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+ db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+ db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+
; Memory tester: writes h ^ l to all addresses from C000 to DF80.
memtest:
ld hl,memteststr
ld sp, $DFF0
-; ld hl, $DF81
-; ld a, $80
-; ld [hl], a
+ ld hl, $DF81
+ ld a, $80
+ ld [hl], a
-; ld c, $07
-; ld a, $07 ;start timer, 4.096KHz
-; ld [c], a
+ ld c, $07
+ ld a, $04 ;start timer, 4.096KHz
+ ld [c], a
;diqs: ei
; ld a, $80
; ld c, $51
; ld [c], a
; jr diqs
call irqhand
+ ei
coqs: jr coqs
section "Diq", HOME[$38]
PUSH DE
PUSH HL
-; ld c, $51
-; ld a, $F0
-; ld [c], a
-
xor a
ld c, $0F ; ack the irq
ld [c], a
- ;ld a, $41 ; print A
- ;call putc
+ ld a, $41 ; print A
+ call putc
-; ld hl, $DF81
-; ld a, [hl]
-; ld b, 1
-; add b
- ld a, $08
- ld hl, $FF51
-; ld c, $51
- nop
- nop
+ ld hl, $DF81
+ ld a, [hl]
+ ld b, 1
+ add b
+ ld c, $51
+ ld [c], a
ld [hl], a
-; ld c, $51
-; ld a, $0F
-; ld [c], a
-
POP HL
POP DE
POP BC
db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+
+putc:
+ ld b, 0
+ ld c, $50
+ push af
+.waitport:
+ ld a,[c]
+ cp b
+ jr nz,.waitport
+ pop af
+ ld [c],a
+ ret