RST insn

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 2e6073ab007a9ad8a92f0e44de70220c85cd813c..82604438fba61afd2e1d93f0f6cd10bdbc272ce1 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 3e15ebf255f473dc239bf89e4b878ad3bcb02087..75f9722adecc13cec3680858096f4b04a7707a9e 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -34,6 +34,7 @@
 `define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
 `define INSN_NOP                               8'b00000000
 `define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
 `define INSN_NOP                               8'b00000000

+`define INSN_RST                               8'b11xxx111

 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000


@@ -338,6 +339,26 @@ module GBZ80Core(
                                `EXEC_NEWCYCLE;
                                `EXEC_INC_PC;
                        end
                                `EXEC_NEWCYCLE;
                                `EXEC_INC_PC;
                        end

+                       `INSN_RST: begin
+                               case (cycle)
+                               0: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               wdata <= registers[`REG_PCH];
+                                       end
+                               1: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                               wdata <= registers[`REG_PCL];
+                                       end
+                               2:      begin /* wee */ end
+                               3: begin
+                                               `EXEC_NEWCYCLE;
+                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                                       {10'b0,opcode[5:3],3'b0};
+                                       end
+                               endcase
+                       end

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase


@@ -563,6 +584,18 @@ module GBZ80Core(
                                end
                        end
                        `INSN_NOP: begin /* NOP! */ end
                                end
                        end
                        `INSN_NOP: begin /* NOP! */ end

+                       `INSN_RST: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      cycle <= 2;
+                               2: cycle <= 3;
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                       end
+                               endcase
+                       end

                        endcase
                        state <= `STATE_FETCH;
                end
                        endcase
                        state <= `STATE_FETCH;
                end

diff --git a/rom.hex b/rom.hex
index a4656313bb550ab895aae56bad41c05c5773452f..b54409e0dc5d05e97a4ce45fe7580a515580d7e3 100644 (file)
--- a/rom.hex
+++ b/rom.hex
@@ -20,8 +20,8 @@ C1
 A8
 // LD (HL), A
 77
 A8
 // LD (HL), A
 77

-// HALT
-76
+// RST 00h
+C7

 
 @100
 02
 
 @100
 02