Start changing things to happen on posedge clock.

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index af173ca63281605658f6f20c97ec4b88fce3a252..f9d71f4c17ef5bff177a5cd0a7b8dd0e3ce01f09 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -21,14 +21,14 @@ module UART(
        reg have_data = 0;
        reg [3:0] diqing = 4'b0000;
        
-       wire new = (wr) && (!have_data) && decode;
+       wire newdata = (wr) && (!have_data) && decode;
        
        assign odata = have_data ? 8'b1 : 8'b0;
 
-       always @ (negedge clk)
+       always @ (posedge clk)
        begin
                /* deal with diqing */
-               if(new) begin
+               if(newdata) begin
                        data_stor <= data;
                        have_data <= 1;
                        diqing <= 4'b0000;
@@ -52,7 +52,7 @@ module UART(
                end
 
                /* deal with clkdiv */
-               if((new && !have_data) || clkdiv == `CLK_DIV)
+               if((newdata && !have_data) || clkdiv == `CLK_DIV)
                        clkdiv <= 0;
                else
                        clkdiv <= clkdiv + 1;